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    MEMORY SYSTEM
    1.
    发明申请
    MEMORY SYSTEM 有权

    公开(公告)号：US20220245028A1

    公开(公告)日：2022-08-04

    申请号：US17464552

    申请日：2021-09-01

    Applicant: KIOXIA CORPORATION

    Inventor： Noboru OKAMOTO ,  Toshikatsu HIDA

    IPC: G06F11/10 ,  G11C16/04 ,  G11C16/20 ,  G11C16/26

    Abstract: A memory system connectable to a host, includes a non-volatile memory including a plurality of memory cell transistors and a controller configured to execute read operations on the non-volatile memory. The controller executes one or more first read operations on the non-volatile memory to obtain read data using read voltages that are determined from one of a plurality of entries stored in a shift table, and performs error correction on the read data, until the error correction is successful, and when the error correction on the read data is successful, records an index corresponding to the entry stored in the shift table that was used in obtaining the successfully error-corrected read data. The controller executes a second read operation on the non-volatile memory to obtain read data using read voltages that are determined from the entry stored in the shift table corresponding to the recorded index.

    MEMORY SYSTEM AND CONTROL METHOD
    3.
    发明申请
    MEMORY SYSTEM AND CONTROL METHOD 有权

    公开(公告)号：US20230073249A1

    公开(公告)日：2023-03-09

    申请号：US17685229

    申请日：2022-03-02

    Applicant: KIOXIA CORPORATION

    Inventor： Suguru NISHIKAWA ,  Toshikatsu HIDA ,  Shunichi IGAHARA ,  Takehiko AMAKI

    IPC: G06F3/06

    Abstract: According to one embodiment, a memory system includes non-volatile memory and volatile memory. A controller encodes a first unit size data portion to be written into the non-volatile memory and generates a first error correction code for the data portion, then writes the data portion into the non-volatile memory. The controller also stores the first error correction code in the volatile memory. When non-volatilization of an error correction code protect the data portion is requested, the controller encodes the data portion to generate a second error correction code for the data portion, and then writes the second error correction code into the non-volatile memory. The second error correction code is smaller in size than the first error correction code.

    MEMORY SYSTEM AND MEMORY SYSTEM CONTROL METHOD
    4.
    发明申请
    MEMORY SYSTEM AND MEMORY SYSTEM CONTROL METHOD 有权

    公开(公告)号：US20220300190A1

    公开(公告)日：2022-09-22

    申请号：US17468895

    申请日：2021-09-08

    Applicant: Kioxia Corporation

    Inventor： Takehiko AMAKI ,  Shunichi IGAHARA ,  Toshikatsu HIDA ,  Yoshihisa KOJIMA ,  Riki SUZUKI

    IPC: G06F3/06

    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller. The nonvolatile memory includes blocks each including memory cells. The memory controller is configured to control access to the nonvolatile memory. The memory controller is configured to: set a first block, among the plurality of blocks, to be written in a first mode, the first mode being a mode in which data of a first number of bits is written into the memory cell, and set a plurality of second blocks, among the plurality of blocks, to be written in a second mode, the second mode being a mode in which data of a second number of bits is written into the memory cell, the second number being larger than the first number; acquire access information related to the second blocks; and change a writing mode of the first block which has been set in the first mode to the second mode when a first condition of the second blocks based on the access information is satisfied.

    MEMORY SYSTEM AND METHOD OF CONTROLLING NONVOLATILE MEMORY
    6.
    发明公开
    MEMORY SYSTEM AND METHOD OF CONTROLLING NONVOLATILE MEMORY 审中-公开

    公开(公告)号：US20240295969A1

    公开(公告)日：2024-09-05

    申请号：US18592763

    申请日：2024-03-01

    Applicant: Kioxia Corporation

    Inventor： Suguru NISHIKAWA ,  Takehiko AMAKI ,  Shunichi IGAHARA ,  Toshikatsu HIDA ,  Yoshihisa KOJIMA

    IPC: G06F3/06

    CPC classification number: G06F3/0619 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679

    Abstract: According to an embodiment, a memory system includes a nonvolatile memory and a memory controller. The nonvolatile memory includes a first memory cell configured to nonvolatilely store data of a plurality of bits including a first bit and a second bit, and a second memory cell configured to nonvolatilely store data of at least one bit. The memory controller is configured to execute a save operation in accordance with reception of a command from a host, in the save operation, write first bit data to the second memory cell in a case where the first memory cell stores the first bit data as the first bit and does not store data as the second bit, and transmit, to the host, a completion response to the command after the first bit data has been written to the second memory cell.

    MEMORY SYSTEM
    8.
    发明申请
    MEMORY SYSTEM 有权

    公开(公告)号：US20210081276A1

    公开(公告)日：2021-03-18

    申请号：US16806131

    申请日：2020-03-02

    Applicant: KIOXIA CORPORATION

    Inventor： Riki SUZUKI ,  Toshikatsu HIDA ,  Yoshihisa KOJIMA ,  Takehiko AMAKI ,  Suguru NISHIKAWA

    IPC: G06F11/10 ,  G06F3/06

    Abstract: A memory system includes a nonvolatile memory, a buffer, and a controller. The buffer can temporarily store a plurality of data bits to be written to the nonvolatile memory. The controller can write the plurality of data bits, read from the buffer, to the nonvolatile memory; write a plurality of intermediate parity bits to the buffer, but not to the nonvolatile memory, wherein each of the plurality of intermediate parity bits is associated with an error correction process on each of the plurality of data bits; and write, to the nonvolatile memory, an accumulated parity bit that is an integration of the plurality of intermediate parity bits.

    MEMORY SYSTEM
    9.
    发明申请
    MEMORY SYSTEM 有权

    公开(公告)号：US20250061954A1

    公开(公告)日：2025-02-20

    申请号：US18936009

    申请日：2024-11-04

    Applicant: Kioxia Corporation

    Inventor： Yoshihisa KOJIMA ,  Shunichi IGAHARA ,  Toshikatsu HIDA

    IPC: G11C16/34 ,  G11C8/00 ,  G11C16/16

    Abstract: According to one embodiment, a memory system includes a non-volatile memory and a memory controller. The non-volatile memory includes a first block that includes first and second sub-blocks. The memory controller instructs the non-volatile memory to execute a data erase process in units of sub-blocks on data stored in the non-volatile memory. In response to a first value corresponding to the first sub-block having reached a first threshold value, the memory controller reads first data from the first sub-block, executes an error correction process on the first data read from the first sub-block, and writes the first data on which the error correction process has been executed into the non-volatile memory.

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