公开(公告)号：US11705443B2

公开(公告)日：2023-07-18

申请号：US17012111

申请日：2020-09-04

Applicant: Kioxia Corporation

Inventor： Hiroshi Maejima ,  Katsuaki Isobe ,  Nobuaki Okada ,  Hiroshi Nakamura ,  Takahiro Tsurudo

IPC: H01L25/18 ,  G11C16/04 ,  G11C16/08 ,  G11C16/26 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L25/18 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  H01L24/08 ,  H01L25/0657 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A semiconductor memory device according to an embodiment includes a substrate, a first memory cell, a first bit line, a first word line, a first transistor, and a second transistor. The first memory cell is provided above the substrate. The first bit line extends in a first direction. The first bit line is coupled to the first memory cell. The first word line extends in a second direction intersecting the first direction. The first word line is coupled to the first memory cell. The first transistor is provided on the substrate. The first transistor is coupled to the first bit line. The second transistor is provided below the first memory cell and on the substrate. The second transistor is coupled to the first word line.

公开(公告)号：US12243598B2

公开(公告)日：2025-03-04

申请号：US18176443

申请日：2023-02-28

Applicant: Kioxia Corporation

Inventor： Yuki Inuzuka ,  Katsuaki Isobe

IPC: G11C16/34 ,  G11C7/06 ,  G11C16/04 ,  G11C16/10

Abstract: A semiconductor storage device includes a bit line, a select gate line, a sense amplifier circuit, a first transistor between the bit line and the sense amplifier circuit, and a second transistor between the bit line and a voltage generation circuit. In a first period of a program operation, the first transistor is turned OFF and the second transistor is turned ON, and a voltage of the first bit line is at a first voltage and a voltage of the select gate line is at a second voltage. In a second period of the program operation, the first transistor is turned ON and the second transistor is turned OFF, and a voltage of the first bit line is at a third voltage less than the first voltage and a voltage of the select gate line is at a fourth voltage greater than the second voltage.

公开(公告)号：US11302398B2

公开(公告)日：2022-04-12

申请号：US17023825

申请日：2020-09-17

Applicant: KIOXIA CORPORATION

Inventor： Katsuaki Isobe ,  Noboru Shibata ,  Toshiki Hisada

IPC: G11C16/16 ,  G11C16/14 ,  G11C16/26 ,  G11C5/02 ,  G11C16/04 ,  H01L27/11519 ,  H01L27/11524 ,  H01L23/528 ,  H01L27/1157 ,  H01L29/10

Abstract: According to one embodiment, a first well of the first conductivity type which is formed in a substrate. a second well of a second conductivity type which is formed in the first well. The plurality of memory cells, the plurality of first bit line select transistors, and the plurality of second bit line select transistors are formed in the second well, and the plurality of first bit line select transistors and the plurality of second bit line select transistors are arranged on a side of the sense amplifier with respect to the plurality of memory cells of the plurality of bit lines.