公开(公告)号：US20250070024A1

公开(公告)日：2025-02-27

申请号：US18811335

申请日：2024-08-21

Applicant: Kioxia Corporation

Inventor： Takafumi MASUDA ,  Mutsumi OKAJIMA ,  Nobuyoshi SAITO ,  Keiji IKEDA

IPC: H01L23/528 ,  H01L23/522 ,  H10B53/10 ,  H10B53/20

Abstract: A semiconductor memory device includes a substrate, first semiconductor layers stacked in a first direction intersecting the substrate, a first via wiring extending in the direction and connected to the layers, memory units stacked in the direction and connected to the layers, first gate electrodes stacked in the direction and facing the layers, first wirings stacked in the direction, extending in a second direction intersecting the first direction, and connected to the first electrodes, second semiconductor layers stacked in the first direction and connected to the first electrodes via the first wirings, a second via wiring extending in the first direction and connected to the second layers, and second gate electrodes stacked in the first direction and facing the second layers. The second layers include a different material from the first layers, or a composition ratio of materials of the second layers is different from that of the first layers.

公开(公告)号：US20240260253A1

公开(公告)日：2024-08-01

申请号：US18423110

申请日：2024-01-25

Applicant: Kioxia Corporation

Inventor： Mutsumi OKAJIMA ,  Takafumi MASUDA ,  Nobuyoshi SAITO ,  Keiji IKEDA

IPC: H10B12/00

CPC classification number: H10B12/30 ,  H10B12/03 ,  H10B12/05

Abstract: A semiconductor memory device comprises: a substrate;
memory layers arranged in a first direction intersecting with a surface of the substrate; and a first via wiring extending in the first direction. The memory layers each comprise: a first semiconductor layer electrically connected to the first via wiring; a first gate electrode facing surfaces on one side and the other side in the first direction of the first semiconductor layer; a memory portion which is provided on one side in a second direction intersecting with the first direction with respect to the first semiconductor layer, and is electrically connected to the first semiconductor layer; and a first wiring which is provided on the other side in the second direction with respect to the first semiconductor layer, is electrically connected to the first gate electrode, and extends in a third direction intersecting with the first direction and the second direction.

公开(公告)号：US20250095692A1

公开(公告)日：2025-03-20

申请号：US18884849

申请日：2024-09-13

Applicant: Kioxia Corporation

Inventor： Takafumi MASUDA ,  Mutsumi OKAJIMA ,  Nobuyoshi SAITO ,  Keiji IKEDA

IPC: G11C5/06 ,  G11C11/22 ,  H10B51/10 ,  H10B51/20

Abstract: A semiconductor memory device includes: a first via-wiring extending in a first direction; first semiconductor layers arranged in the first direction and electrically connected to the first via-wiring; memory portions arranged in the first direction and electrically connected to the first semiconductor layers; first gate electrodes arranged in the first direction and opposed to the plurality of first semiconductor layers; first wirings arranged in the first direction and electrically connected to the plurality of first gate electrodes; second semiconductor layers arranged in the first direction and electrically connected to the first wirings; second gate electrodes arranged in the first direction and opposed to the second semiconductor layers; a second via-wiring extending in the first direction and electrically connected to the plurality of second gate electrodes; and second wirings arranged in the first direction and electrically connected to the second semiconductor layers.

公开(公告)号：US20240081042A1

公开(公告)日：2024-03-07

申请号：US18459978

申请日：2023-09-01

Applicant: Kioxia Corporation

Inventor： Takafumi MASUDA ,  Mutsumi OKAJIMA ,  Nobuyoshi SAITO ,  Keiji IKEDA

IPC: H10B12/00

CPC classification number: H10B12/30 ,  H10B12/02

Abstract: A semiconductor memory device comprises: a first memory layer; and a first via wiring and a second via wiring extending in a first direction, and having different positions from each other in a second direction. The first memory layer comprises: a first transistor electrically connected to the first via wiring; a memory portion electrically connected to the first transistor; a first wiring electrically connected to the first transistor; a second transistor electrically connected to the second via wiring and the first wiring; a first electrode electrically connected to the second transistor; and a second electrode electrically connected to the first wiring and first electrode. A length of the second electrode in the first direction is larger than one or both of a length of the first wiring in the first direction and a length of the first conductive layer in the first direction.

公开(公告)号：US20240324174A1

公开(公告)日：2024-09-26

申请号：US18605986

申请日：2024-03-15

Applicant: Kioxia Corporation

Inventor： Takafumi MASUDA ,  Mutsumi OKAJIMA ,  Nobuyoshi SAITO ,  Keiji IKEDA

IPC: H10B12/00

CPC classification number: H10B12/30 ,  H10B12/03 ,  H10B12/05

Abstract: A semiconductor memory device includes memory layers arranged in a first direction and a via-wiring extending in the first direction. The plurality of memory layers each include a semiconductor layer electrically connected to the via-wiring, a gate electrode opposed to surfaces of the semiconductor layer in the first direction, a memory portion disposed on one side in a second direction with respect to the semiconductor layer, a wiring disposed on the other side in the second direction with respect to the semiconductor layer, and a connection wiring connected to the gate electrode and the wiring. The connection wiring includes a first part extending in the second direction along a side surface of the gate electrode in the third direction and a second part continuous with the first part, extending in the third direction along a side surface of the wiring in the second direction.

公开(公告)号：US20240312911A1

公开(公告)日：2024-09-19

申请号：US18601745

申请日：2024-03-11

Applicant: Kioxia Corporation

Inventor： Takafumi MASUDA ,  Mutsumi OKAJIMA ,  Nobuyoshi SAITO ,  Keiji IKEDA

IPC: H01L23/528 ,  H01L23/522 ,  H10B12/00

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H01L23/528 ,  H10B12/315 ,  H10B12/482

Abstract: A semiconductor memory device includes a memory layer and a via-wiring extending in a first direction. The memory layer includes a semiconductor layer electrically connected to the via-wiring, a gate electrode including parts opposed to surfaces of the semiconductor layer on one side and the other side in the first direction, a memory portion disposed on one side in a second direction with respect to the semiconductor layer, and a wiring disposed on the other side in the second direction with respect to the semiconductor layer. In a cross-sectional surface perpendicular to the first direction and including one of the parts of the gate electrode, the via-wiring includes a surface opposed to the gate electrode and a surface not opposed to the gate electrode. A part of the gate electrode is disposed on a memory portion side with respect to the via-wiring in the second direction.

公开(公告)号：US20240087616A1

公开(公告)日：2024-03-14

申请号：US18463686

申请日：2023-09-08

Applicant: Kioxia Corporation

Inventor： Takafumi MASUDA ,  Nobuyoshi SAITO ,  Mutsumi OKAJIMA ,  Keiji IKEDA

IPC: G11C5/06 ,  G11C5/10

CPC classification number: G11C5/063 ,  G11C5/10

Abstract: A semiconductor memory device comprises: memory layers arranged in a first direction; and a first and a second via wirings having different positions in a second direction. The memory layer comprises: a first transistor electrically connected to the first via wiring; a memory portion electrically connected to the first transistor; a wiring electrically connected to the first transistor; a second transistor electrically connected to the second via wiring; and an electrode provided in a current path between the second transistor and the wiring. The second transistor comprises: a semiconductor layer electrically connected to the electrode and the second via wiring; and a gate electrode facing the semiconductor layer. The semiconductor layer faces at least one of surfaces on one side or the other side in the first direction of the gate electrode. The electrode includes a portion arranged with the second via wiring in a third direction.

公开(公告)号：US20240038280A1

公开(公告)日：2024-02-01

申请号：US18184792

申请日：2023-03-16

Applicant: Kioxia Corporation

Inventor： Takafumi MASUDA ,  Mutsumi OKAJIMA ,  Nobuyoshi SAITO ,  Keiji IKEDA

IPC: G11C5/10 ,  G11C11/4097 ,  G11C11/4096

CPC classification number: G11C5/10 ,  G11C11/4097 ,  G11C11/4096

Abstract: A semiconductor memory device comprises: memory layers arranged in a first direction; and a first wiring extending in the first direction. The memory layers each comprise: a memory portion; a transistor; and a second wiring. The transistor comprises: a semiconductor layer electrically connected between the memory portion and the first wiring; a gate electrode facing the semiconductor layer and electrically connected to the second wiring; and a gate insulating film provided between the semiconductor layer and the gate electrode. The semiconductor layer faces surfaces of the gate electrode on one side and the other side in the first direction. In a cross section perpendicular to the first direction and including a part of the transistor corresponding to one of the memory layers, the first wiring comprises: a first surface in contact with the transistor; and a second surface not in contact with the transistor.