公开(公告)号：US20240087656A1

公开(公告)日：2024-03-14

申请号：US18332753

申请日：2023-06-12

Applicant: Kioxia Corporation

Inventor： Katsuaki ISOBE ,  Takeshi HIOKA ,  Mario SAKO

IPC: G11C16/26 ,  G11C16/04

CPC classification number: G11C16/26 ,  G11C16/0483

Abstract: A semiconductor memory device includes a first memory cell transistor, a first bit line electrically coupled to the first memory cell transistor, a first sense amplifier, and a first latch circuit. The first sense amplifier includes a first node coupled to the first bit line, a first transistor including one end electrically coupled to the first latch circuit, a second node coupled to a gate of the first transistor, and a second transistor coupled between the first and second nodes. The second transistor is in an ON state during an operation of transferring a charge from the first bit line to the first and second nodes in accordance with data of the first memory cell transistor. The second transistor is in an OFF state during an operation of transferring data of the second node to the first latch circuit.

公开(公告)号：US20240096417A1

公开(公告)日：2024-03-21

申请号：US18337605

申请日：2023-06-20

Applicant: Kioxia Corporation

Inventor： Hiroshi MAEJIMA ,  Katsuaki ISOBE ,  Keita KIMURA

IPC: G11C16/04 ,  G11C5/06 ,  G11C16/14 ,  G11C16/26

CPC classification number: G11C16/0483 ,  G11C5/063 ,  G11C16/14 ,  G11C16/26

Abstract: In one embodiment, a semiconductor storage device includes a string that has one end electrically connected to a bit line, and another end electrically connected to a source line, and includes a plurality of memory cells. An operation of writing data to each of a plurality of adjacent first memory cells among the plurality of memory cells is sequentially performed in a direction from a first memory cell on a side of the source line to a first memory cell on a side of the bit line. An operation of reading data from each of the plurality of adjacent first memory cells is performed to allow a current to flow through the string in a first direction from the source line to the bit line.

公开(公告)号：US20210118862A1

公开(公告)日：2021-04-22

申请号：US17012111

申请日：2020-09-04

Applicant: Kioxia Corporation

Inventor： Hiroshi MAEJIMA ,  Katsuaki ISOBE ,  Nobuaki OKADA ,  Hiroshi NAKAMURA ,  Takahiro TSURUDO

IPC: H01L25/18 ,  G11C16/04 ,  G11C16/08 ,  G11C16/26 ,  H01L25/065 ,  H01L23/00

Abstract: A semiconductor memory device according to an embodiment includes a substrate, a first memory cell, a first bit line, a first word line, a first transistor, and a second transistor. The first memory cell is provided above the substrate. The first bit line extends in a first direction. The first bit line is coupled to the first memory cell. The first word line extends in a second direction intersecting the first direction. The first word line is coupled to the first memory cell. The first transistor is provided on the substrate. The first transistor is coupled to the first bit line. The second transistor is provided below the first memory cell and on the substrate. The second transistor is coupled to the first word line.

公开(公告)号：US20240324216A1

公开(公告)日：2024-09-26

申请号：US18597150

申请日：2024-03-06

Applicant: Kioxia Corporation

Inventor： Hiroyuki YAMASAKI ,  Masayoshi TAGAMI ,  Katsuaki ISOBE

IPC: H10B43/27 ,  H01L25/065 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B43/27 ,  H01L25/0657 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40

Abstract: According to one embodiment, in a semiconductor memory device including a first chip and a second chip. The first chip includes a first stacked body, a first semiconductor film, a second stacked body, a second semiconductor film, a contact plug and a first planar wiring line. The contact plug extends in the third direction between the first stacked body and the second stacked body. The first planar wiring line is disposed on a side opposite to the second chip with respect to the first stacked body, the contact plug, and the second stacked body, the first planar wiring line extending in the first direction and the second direction, covering at least the contact plug, and being connected to the contact plug.

公开(公告)号：US20240029807A1

公开(公告)日：2024-01-25

申请号：US18176443

申请日：2023-02-28

Applicant: Kioxia Corporation

Inventor： Yuki INUZUKA ,  Katsuaki ISOBE

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/04 ,  G11C7/06

CPC classification number: G11C16/3459 ,  G11C16/102 ,  G11C16/0433 ,  G11C7/067

Abstract: A semiconductor storage device includes a bit line, a select gate line, a sense amplifier circuit, a first transistor between the bit line and the sense amplifier circuit, and a second transistor between the bit line and a voltage generation circuit. In a first period of a program operation, the first transistor is turned OFF and the second transistor is turned ON, and a voltage of the first bit line is at a first voltage and a voltage of the select gate line is at a second voltage. In a second period of the program operation, the first transistor is turned ON and the second transistor is turned OFF, and a voltage of the first bit line is at a third voltage less than the first voltage and a voltage of the select gate line is at a fourth voltage greater than the second voltage.

公开(公告)号：US20230307434A1

公开(公告)日：2023-09-28

申请号：US18203952

申请日：2023-05-31

Applicant: Kioxia Corporation

Inventor： Hiroshi MAEJIMA ,  Katsuaki ISOBE ,  Nobuaki OKADA ,  Hiroshi NAKAMURA ,  Takahiro TSURUDO

IPC: H01L25/18 ,  G11C16/04 ,  G11C16/08 ,  G11C16/26 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L25/18 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  H01L24/08 ,  H01L25/0657 ,  H01L2924/14511 ,  H01L2224/08145 ,  H01L2924/1431

Abstract: A semiconductor memory device according to an embodiment includes a substrate, a first memory cell, a first bit line, a first word line, a first transistor, and a second transistor. The first memory cell is provided above the substrate. The first bit line extends in a first direction. The first bit line is coupled to the first memory cell. The first word line extends in a second direction intersecting the first direction. The first word line is coupled to the first memory cell. The first transistor is provided on the substrate. The first transistor is coupled to the first bit line. The second transistor is provided below the first memory cell and on the substrate. The second transistor is coupled to the first word line.