公开(公告)号：US5145800A

公开(公告)日：1992-09-08

申请号：US731616

申请日：1991-07-17

申请人： Kiyokazu Arai ,  Masatoshi Kawashima ,  Akira Yamagiwa ,  Toshihiro Okabe

发明人： Kiyokazu Arai ,  Masatoshi Kawashima ,  Akira Yamagiwa ,  Toshihiro Okabe

IPC分类号： H01L21/822 ,  H01L21/82 ,  H01L23/528 ,  H01L27/04 ,  H01L27/118

CPC分类号： H01L23/5286 ,  H01L2924/0002

摘要： A method for wiring a power supply for a large-scale integrated circuit. The power supply wires define a power supply grid surrounding lattice openings with fixed longitudinal and transverse lattice dimensions. The wire width is determined based on the integrated circuit chip size, the number of function circuits to be on the integrated circuit, the electrical power requirements of the function circuits, and the fixed longitudinal and transverse lattice dimensions. Longitudinal and transverse locations of the power supply wires chips are determined based on the determined wire width and the fixed longitudinal and transverse dimensions of the lattice openings. Alternatively, the wire width may be fixed and the dimensions of the lattice openings determined based on the integrated circuit chip size, the number of function circuits, the electrical power requirements of the function circuits and that wire width. When the electrical power requirement of a function circuit is significantly larger than that of another function circuit, the wire width may be increased in the vicinity of the one function circuit. When the function circuits include a large-scale function block, a wire width around a region of the integrated circuit chip in which the large-scale block is to be disposed may be selected which results in a wire area equal to the wire area of the power supply wire that would occupy the particular region for usual function circuits.

摘要翻译： 一种用于大规模集成电路的电源接线的方法。 电源线定义了围绕具有固定的纵向和横向晶格尺寸的格栅开口的电源网格。 线宽是基于集成电路芯片尺寸，集成电路上的功能电路的数量，功能电路的电功率要求以及固定的纵向和横向晶格尺寸来确定的。 电源线芯片的纵向和横向位置基于确定的线宽度和格子孔的固定纵向和横向尺寸来确定。 或者，线宽可以是固定的，并且基于集成电路芯片尺寸，功能电路的数量，功能电路的电功率要求和线宽度确定的格子孔的尺寸。 当功能电路的电力需求明显大于另一个功能电路的电力需求时，可以在一个功能电路附近增加导线宽度。 当功能电路包括大规模功能块时，可以选择其中要布置大规模块的集成电路芯片的区域周围的导线宽度，这导致导线面积等于 将占用特定区域用于通常功能电路的电源线。

公开(公告)号：US5452436A

公开(公告)日：1995-09-19

申请号：US367927

申请日：1995-01-03

申请人： Kiyokazu Arai ,  Akira Yamagiwa ,  Toshihiro Okabe

发明人： Kiyokazu Arai ,  Akira Yamagiwa ,  Toshihiro Okabe

IPC分类号： G06F13/42 ,  G06F1/10 ,  G06F13/00 ,  H04L7/00 ,  H04L12/40 ,  G06F1/04

CPC分类号： G06F1/10 ,  H04L7/0008

摘要： A data processing apparatus, including a number of electronic circuit units, in which high-speed data can be transmitted among the electronic circuit units. When data is transmitted from one electronic circuit unit to another electronic circuit unit, a clock signal to fetch the data in the sink side electronic circuit unit is transmitted from the source side electronic circuit unit via a clock signal line having the same signal propagation delay characteristics as those of the data signal line.

摘要翻译： 一种数据处理装置，包括多个电子电路单元，其中可以在电子电路单元之间传输高速数据。 当从一个电子电路单元发送数据到另一个电子电路单元时，通过具有相同信号传播延迟特性的时钟信号线从源极侧电子单元发送用于取出接收侧电子电路单元中的数据的时钟信号 作为数据信号线的那些。

公开(公告)号：US4903267A

公开(公告)日：1990-02-20

申请号：US126834

申请日：1987-11-30

申请人： Kiyokazu Arai ,  Syun Ishiyama

发明人： Kiyokazu Arai ,  Syun Ishiyama

IPC分类号： H01L21/66 ,  G01R31/28 ,  G01R31/3183 ,  G01R31/319

CPC分类号： G01R31/318307 ,  G01R31/31908

摘要： The invention prepares test data on a logic LSI which includes a plurality of signal pins, a control pin for inputting an external control signal, and control circuitry responsive to the external control signal for setting the signal pins in a desired state according to a specified function thereof.In accordance with the invention, the method comprises the steps of storing first data in a first memory, the first data being representative of a specified function of individual pins; storing the second data in a second memory, the second data representing a plurality of pin states corresponding to a plurality of signal states set by the external control signal; reading first and second data from the first and second memory; selectively communicating the test control signal to the integrated circuit, generating third data representative of each pin state of individual pins of each signal state set by the external control signal; and storing the third data into a file as test data.

摘要翻译： 本发明在逻辑LSI上准备测试数据，逻辑LSI包括多个信号引脚，用于输入外部控制信号的控制引脚，以及响应于外部控制信号的控制电路，用于根据指定的功能将信号引脚设置在期望的状态 其中。 根据本发明，该方法包括以下步骤：将第一数据存储在第一存储器中，第一数据代表各个引脚的指定功能; 将所述第二数据存储在第二存储器中，所述第二数据表示与由所述外部控制信号设置的多个信号状态相对应的多个引脚状态; 从第一和第二存储器读取第一和第二数据; 选择性地将测试控制信号传送到集成电路，产生表示由外部控制信号设置的每个信号状态的各个引脚的每个引脚状态的第三数据; 并将第三数据存储到文件中作为测​​试数据。