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    Method of wiring for power supply to large-scale integrated circuit
    1.
    发明授权
    Method of wiring for power supply to large-scale integrated circuit 失效
    大规模集成电路供电方式

    公开(公告)号：US5145800A

    公开(公告)日：1992-09-08

    申请号：US731616

    申请日：1991-07-17

    申请人： Kiyokazu Arai ,  Masatoshi Kawashima ,  Akira Yamagiwa ,  Toshihiro Okabe

    发明人： Kiyokazu Arai ,  Masatoshi Kawashima ,  Akira Yamagiwa ,  Toshihiro Okabe

    IPC分类号： H01L21/822 ,  H01L21/82 ,  H01L23/528 ,  H01L27/04 ,  H01L27/118

    CPC分类号： H01L23/5286 ,  H01L2924/0002

    摘要： A method for wiring a power supply for a large-scale integrated circuit. The power supply wires define a power supply grid surrounding lattice openings with fixed longitudinal and transverse lattice dimensions. The wire width is determined based on the integrated circuit chip size, the number of function circuits to be on the integrated circuit, the electrical power requirements of the function circuits, and the fixed longitudinal and transverse lattice dimensions. Longitudinal and transverse locations of the power supply wires chips are determined based on the determined wire width and the fixed longitudinal and transverse dimensions of the lattice openings. Alternatively, the wire width may be fixed and the dimensions of the lattice openings determined based on the integrated circuit chip size, the number of function circuits, the electrical power requirements of the function circuits and that wire width. When the electrical power requirement of a function circuit is significantly larger than that of another function circuit, the wire width may be increased in the vicinity of the one function circuit. When the function circuits include a large-scale function block, a wire width around a region of the integrated circuit chip in which the large-scale block is to be disposed may be selected which results in a wire area equal to the wire area of the power supply wire that would occupy the particular region for usual function circuits.

    摘要翻译： 一种用于大规模集成电路的电源接线的方法。 电源线定义了围绕具有固定的纵向和横向晶格尺寸的格栅开口的电源网格。 线宽是基于集成电路芯片尺寸，集成电路上的功能电路的数量，功能电路的电功率要求以及固定的纵向和横向晶格尺寸来确定的。 电源线芯片的纵向和横向位置基于确定的线宽度和格子孔的固定纵向和横向尺寸来确定。 或者，线宽可以是固定的，并且基于集成电路芯片尺寸，功能电路的数量，功能电路的电功率要求和线宽度确定的格子孔的尺寸。 当功能电路的电力需求明显大于另一个功能电路的电力需求时，可以在一个功能电路附近增加导线宽度。 当功能电路包括大规模功能块时，可以选择其中要布置大规模块的集成电路芯片的区域周围的导线宽度，这导致导线面积等于 将占用特定区域用于通常功能电路的电源线。

    Variable delay circuit and clock signal supply unit using the same
    3.
    发明授权
    Variable delay circuit and clock signal supply unit using the same 失效
    可变延迟电路和时钟信号供给单元使用相同

    公开(公告)号：US5497263A

    公开(公告)日：1996-03-05

    申请号：US117525

    申请日：1993-09-07

    申请人： Noboru Masuda ,  Kazumichi Yamamoto ,  Kazunori Nakajima ,  Toshihiro Okabe ,  Akira Yamagiwa ,  Mikio Yamagishi ,  Kazuo Koide ,  Bunichi Fujita ,  Seiichi Kawashima

    发明人： Noboru Masuda ,  Kazumichi Yamamoto ,  Kazunori Nakajima ,  Toshihiro Okabe ,  Akira Yamagiwa ,  Mikio Yamagishi ,  Kazuo Koide ,  Bunichi Fujita ,  Seiichi Kawashima

    IPC分类号： G06F1/06 ,  G06F1/10 ,  G11C11/407 ,  G11C11/4076 ,  H03K5/00 ,  H03K5/13 ,  H03K5/131 ,  H03H11/26 ,  H03K17/296

    CPC分类号： H03K5/133 ,  G06F1/10 ,  H03K2005/00071 ,  H03K2005/00097 ,  H03K2005/00195

    摘要： A variable delay circuit including delay devices each having a plurality of delay units connected successively, only some of the delay units of the delay devices being connected to a signal transmission line, wherein a delay time is controlled by activating or inactivating the plurality of delay units according to control signals applied to control input terminals provided respectively for said plurality of delay units. A clock signal supply device for supplying a second clock signal to a logic circuit block, said clock signal supply device having a clock signal generator for generating a first clock signal and a reference signal and a phase adjusting means for adjusting the phase of the first clock signal phased on a phase difference between the first clock signal and the reference signal and outputting the phase-adjusted signal as a second clock signal, wherein the phase adjusting unit comprises a first variable delay circuit capable of delay operation in initial adjustment of the first clock signal, a second variable delay circuit, disposed in series with the first variable delay circuit, for performing the delay operation after the initial adjustment, and control circuits for controlling delay times of the first and second variable delay circuits.

    摘要翻译： 一种可变延迟电路，包括延迟装置，每个延迟装置具有连续连接的多个延迟单元，延迟装置的一些延迟单元连接到信号传输线，其中通过激活或者使多个延迟单元激活来控制延迟时间 根据施加到分别为所述多个延迟单元提供的控制输入端子的控制信号。 一种用于向逻辑电路块提供第二时钟信号的时钟信号提供装置，所述时钟信号提供装置具有用于产生第一时钟信号和参考信号的时钟信号发生器和用于调整第一时钟的相位的相位调整装置 信号相位于第一时钟信号和参考信号之间的相位差，并输出相位调整信号作为第二时钟信号，其中相位调整单元包括能够在第一时钟的初始调整中延迟操作的第一可变延迟电路 信号，与第一可变延迟电路串联布置的第二可变延迟电路，用于在初始调整之后执行延迟操作;以及控制电路，用于控制第一和第二可变延迟电路的延迟时间。

    Multiphase clock distribution for VLSI chip
    4.
    发明授权
    Multiphase clock distribution for VLSI chip 失效
    VLSI芯片的多相时钟分配

    公开(公告)号：US4812684A

    公开(公告)日：1989-03-14

    申请号：US146864

    申请日：1988-01-22

    申请人： Akira Yamagiwa ,  Toshihiro Okabe

    发明人： Akira Yamagiwa ,  Toshihiro Okabe

    IPC分类号： H01L27/088 ,  G06F1/04 ,  G06F1/10 ,  G06F15/78 ,  G06F17/50 ,  G11C11/401 ,  H01L21/8234 ,  H03K5/15 ,  H03K19/00 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/096

    CPC分类号： G06F1/10 ,  H03K19/00323

    摘要： Multi-phase clock signals are delivered to a large number of load circuits scattered on a chip from clock signal input pins through at least three stage buffer circuits. The first stage buffer circuits are arranged in the neighborhood of the input pins, and the second stage buffer circuits are arranged on the central portion of the chip. Equivalent-length wirings are made between the successive two stage buffer circuits and the same number of subsequent stage buffer circuit are connected with each of certain stage buffer circuits for the respective phases so as to provide equal resistances and equal capacitances. Equivalent-length wirings are also made between final stage buffer circuits and the corresponding load circuits, and the same number of load circuits are connected with each final stage buffer circuit. Thus, equal delay times are provided in the clock signal paths from the input pins to the load circuits at the respective phases.

    摘要翻译： 多相时钟信号通过至少三级缓冲电路从时钟信号输入引脚传送到分散在芯片上的大量负载电路。 第一级缓冲电路布置在输入引脚附近，第二级缓冲电路布置在芯片的中心部分。 在连续的两级缓冲电路之间进行等效长度布线，并且相同数量的后级缓冲电路与各相的各级缓冲电路连接，以提供相等的电阻和相等的电容。 最终级缓冲电路和相应的负载电路之间也有等长线，并且每个最后级缓冲电路连接相同数量的负载电路。 因此，在从各个相位的输入引脚到负载电路的时钟信号路径中提供相等的延迟时间。

    High speed clock distribution system
    5.
    发明授权
    High speed clock distribution system 失效
    高速时钟分配系统

    公开(公告)号：US5087829A

    公开(公告)日：1992-02-11

    申请号：US443503

    申请日：1989-12-01

    申请人： Kenichi Ishibashi ,  Takehisa Hayashi ,  Toshio Doi ,  Mitsuo Asai ,  Noboru Masuda ,  Akira Yamagiwa ,  Toshihiro Okabe

    发明人： Kenichi Ishibashi ,  Takehisa Hayashi ,  Toshio Doi ,  Mitsuo Asai ,  Noboru Masuda ,  Akira Yamagiwa ,  Toshihiro Okabe

    IPC分类号： H03K5/15

    CPC分类号： H03K5/15

    摘要： This invention discloses a clock distribution system which distributes a first clock signal as a reference clock as the reference for the phase and frequency to each processing unit (e.g. LSI) and generates a multi-phase second clock signal to be used in each processing unit by a delay circuit group whose delay time is adjusted. The clock distribution system comprises a clock generation block for generating a one-phase reference clock; a first control loop for comparing the phase of the reference clock with the phase of a feedback signal and adjusting the phase of the reference clock so that their phases are in agreement; and a second control loop including a delay circuit group consisting of a plurality of variable delay circuits to which the reference clock phase-adjusted by the first control loop is inputted and which are connected in series, and means for generating a multi-phase clock signal by use of the output signal of each of the plurality of variable delay circuits and the phase-adjusted referencde clock, controlling the delay time of the plurality of variable delay circuits so as to accomplish a predetermined relation with the period of the phase-adjusted reference clock and applying one of the multi-phase clock signals as the feedback signal described above to the first control loop.

    摘要翻译： 本发明公开了一种时钟分配系统，其将作为基准时钟的第一时钟信号作为相位和频率的参考分配给每个处理单元（例如，LSI），并且通过以下方式生成要在每个处理单元中使用的多相第二时钟信号： 延迟时间被调整的延迟电路组。 时钟分配系统包括用于产生单相参考时钟的时钟产生模块; 第一控制环路，用于将参考时钟的相位与反馈信号的相位进行比较，并且调整参考时钟的相位，使得它们的相位一致; 以及包括由多个可变延迟电路组成的延迟电路组的第二控制回路，所述多个可变延迟电路输入由第一控制回路相位调整的参考时钟并串联连接的参考时钟，以及用于产生多相时钟信号的装置 通过使用多个可变延迟电路中的每一个的输出信号和相位调整参考时钟，控制多个可变延迟电路的延迟时间，以便与相位调整参考的周期完成预定的关系 时钟，并将多相时钟信号中的一个作为上述反馈信号施加到第一控制回路。

    Signal transmitting device suited to fast signal transmission
    6.
    发明授权
    Signal transmitting device suited to fast signal transmission 失效
    信号传输设备适合快速信号传输

    公开(公告)号：US07911224B2

    公开(公告)日：2011-03-22

    申请号：US12116541

    申请日：2008-05-07

    申请人： Toshitsugu Takekuma ,  Ryoichi Kurihara ,  Akira Yamagiwa

    发明人： Toshitsugu Takekuma ,  Ryoichi Kurihara ,  Akira Yamagiwa

    IPC分类号： H03K19/003

    CPC分类号： H04L25/0298 ,  G06F13/4072 ,  G06F13/4086 ,  H04B3/02 ,  H04L25/0278 ,  H04L25/028 ,  H04L25/0292 ,  H05K1/0216 ,  H05K1/0237 ,  H05K1/14

    摘要： A signal transmitting circuit includes a circuit block having a driving circuit and an intra-block transmission line for transmitting a signal from the driving circuit, a circuit block having a receiving circuit and an intra-block transmission line for transmitting the signal to said receiving circuit, and a main interblock transmission line for propagating a signal between the driving and receiving circuit blocks. The inter-block transmission line is terminated by a resistor having substantially the same impedance as the interblock transmission line. The intra-block transmission lines are provided with a resistance element having a resistance substantially equal to a value derived by subtracting half of an impedance of the inter-block transmission line from an impedance of the intra-block transmission line, to lower signal amplitude and suppress reflections of a signal at branch points along the main interblock transmission line, thereby enabling a high-speed signal transfer.

    摘要翻译： 信号发送电路包括具有用于发送来自驱动电路的信号的驱动电路和块内传输线路的电路块，具有接收电路的电路块和用于将信号发送到所述接收电路的块内传输线路 以及用于在驱动和接收电路块之间传播信号的主块间传输线。 块间​​传输线由具有与块间传输线基本上相同阻抗的电阻端接。 块内传输线路设置有电阻元件，其电阻基本上等于通过将块间传输线路的阻抗的一半从块内传输线路的阻抗减去一半到更低的信号幅度， 抑制沿着主块间传输线的分支点处的信号的反射，从而实现高速信号传送。

    Signal transmitting device suited to fast signal transmission
    7.
    发明授权
    Signal transmitting device suited to fast signal transmission 有权

    公开(公告)号：US07123048B2

    公开(公告)日：2006-10-17

    申请号：US11049663

    申请日：2005-02-04

    申请人： Toshitsuqu Takekuma ,  Ryoichi Kurihara ,  Akira Yamagiwa

    发明人： Toshitsuqu Takekuma ,  Ryoichi Kurihara ,  Akira Yamagiwa

    IPC分类号： H03K17/16

    CPC分类号： H04L25/0298 ,  G06F13/4072 ,  G06F13/4086 ,  H04B3/02 ,  H04L25/0278 ,  H04L25/028 ,  H04L25/0292 ,  H05K1/0216 ,  H05K1/0237 ,  H05K1/14

    摘要： A signal transmitting circuit includes a circuit block having a driving circuit and an intra-block transmission line for transmitting a signal from the driving circuit, a circuit block having a receiving circuit and an intra-block transmission line for transmitting the signal to said receiving circuit, and a main interblock transmission line for propagating a signal between the driving and receiving circuit blocks. The inter-block transmission line is terminated by a resistor having substantially the same impedance as the interblock transmission line. The intra-block transmission lines are provided with a resistance element having a resistance substantially equal to a value derived by subtracting half of an impedance of the inter-block transmission line from an impedance of the intra-block transmission line, to lower signal amplitude and suppress reflections of a signal at branch points along the main interblock transmission line, thereby enabling a high-speed signal transfer.

    Branch bus system for inter-LSI data transmission
    10.
    发明授权
    Branch bus system for inter-LSI data transmission 失效
    分支总线系统，用于LSI间数据传输

    公开(公告)号：US06766404B1

    公开(公告)日：2004-07-20

    申请号：US09568055

    申请日：2000-05-10

    申请人： Hideki Osaka ,  Akira Yamagiwa ,  Kenichi Ishibashi

    发明人： Hideki Osaka ,  Akira Yamagiwa ,  Kenichi Ishibashi

    IPC分类号： G06F100

    CPC分类号： H04L25/0278 ,  G06F13/4077

    摘要： A fast transfer bus system capable of fast data transfer with no reflection at branch points. Four LSIs having constant-impedance interfaces are connected via two variable resistors each having three signal terminals. A variable impedance LSI is connected between these variable resistors. When the LSIs connected to the variable resistor do not work as a bus driver, three variable resistance elements in each variable resistor are set to have a value of ⅓ of the characteristic impedance Zo of connection lines, and are connected in a Y-letter shape. When one of LSIs connected to the variable resistor works as a bus driver, the values of the variable resistance elements are set to low impedance or Zo.

    摘要翻译： 快速传输总线系统，能够快速传输数据，在分支点无反射。 具有恒定阻抗接口的四个LSI通过两个可变电阻器连接，每个可变电阻器具有三个信号端子。 可变阻抗LSI连接在这些可变电阻之间。 当连接到可变电阻器的LSI不能用作总线驱动器时，每个可变电阻器中的三个可变电阻元件被设置为连接线的特性阻抗Zo的1/3，并且以Y- 字母形状。 当连接到可变电阻器的LSI中的一个作为总线驱动器工作时，可变电阻元件的值被设置为低阻抗或Zo。