公开(公告)号：US5452436A

公开(公告)日：1995-09-19

申请号：US367927

申请日：1995-01-03

申请人： Kiyokazu Arai ,  Akira Yamagiwa ,  Toshihiro Okabe

发明人： Kiyokazu Arai ,  Akira Yamagiwa ,  Toshihiro Okabe

IPC分类号： G06F13/42 ,  G06F1/10 ,  G06F13/00 ,  H04L7/00 ,  H04L12/40 ,  G06F1/04

CPC分类号： G06F1/10 ,  H04L7/0008

摘要： A data processing apparatus, including a number of electronic circuit units, in which high-speed data can be transmitted among the electronic circuit units. When data is transmitted from one electronic circuit unit to another electronic circuit unit, a clock signal to fetch the data in the sink side electronic circuit unit is transmitted from the source side electronic circuit unit via a clock signal line having the same signal propagation delay characteristics as those of the data signal line.

摘要翻译： 一种数据处理装置，包括多个电子电路单元，其中可以在电子电路单元之间传输高速数据。 当从一个电子电路单元发送数据到另一个电子电路单元时，通过具有相同信号传播延迟特性的时钟信号线从源极侧电子单元发送用于取出接收侧电子电路单元中的数据的时钟信号 作为数据信号线的那些。

公开(公告)号：US5145800A

公开(公告)日：1992-09-08

申请号：US731616

申请日：1991-07-17

申请人： Kiyokazu Arai ,  Masatoshi Kawashima ,  Akira Yamagiwa ,  Toshihiro Okabe

发明人： Kiyokazu Arai ,  Masatoshi Kawashima ,  Akira Yamagiwa ,  Toshihiro Okabe

IPC分类号： H01L21/822 ,  H01L21/82 ,  H01L23/528 ,  H01L27/04 ,  H01L27/118

CPC分类号： H01L23/5286 ,  H01L2924/0002

摘要： A method for wiring a power supply for a large-scale integrated circuit. The power supply wires define a power supply grid surrounding lattice openings with fixed longitudinal and transverse lattice dimensions. The wire width is determined based on the integrated circuit chip size, the number of function circuits to be on the integrated circuit, the electrical power requirements of the function circuits, and the fixed longitudinal and transverse lattice dimensions. Longitudinal and transverse locations of the power supply wires chips are determined based on the determined wire width and the fixed longitudinal and transverse dimensions of the lattice openings. Alternatively, the wire width may be fixed and the dimensions of the lattice openings determined based on the integrated circuit chip size, the number of function circuits, the electrical power requirements of the function circuits and that wire width. When the electrical power requirement of a function circuit is significantly larger than that of another function circuit, the wire width may be increased in the vicinity of the one function circuit. When the function circuits include a large-scale function block, a wire width around a region of the integrated circuit chip in which the large-scale block is to be disposed may be selected which results in a wire area equal to the wire area of the power supply wire that would occupy the particular region for usual function circuits.

摘要翻译： 一种用于大规模集成电路的电源接线的方法。 电源线定义了围绕具有固定的纵向和横向晶格尺寸的格栅开口的电源网格。 线宽是基于集成电路芯片尺寸，集成电路上的功能电路的数量，功能电路的电功率要求以及固定的纵向和横向晶格尺寸来确定的。 电源线芯片的纵向和横向位置基于确定的线宽度和格子孔的固定纵向和横向尺寸来确定。 或者，线宽可以是固定的，并且基于集成电路芯片尺寸，功能电路的数量，功能电路的电功率要求和线宽度确定的格子孔的尺寸。 当功能电路的电力需求明显大于另一个功能电路的电力需求时，可以在一个功能电路附近增加导线宽度。 当功能电路包括大规模功能块时，可以选择其中要布置大规模块的集成电路芯片的区域周围的导线宽度，这导致导线面积等于 将占用特定区域用于通常功能电路的电源线。

公开(公告)号：US4812684A

公开(公告)日：1989-03-14

申请号：US146864

申请日：1988-01-22

申请人： Akira Yamagiwa ,  Toshihiro Okabe

发明人： Akira Yamagiwa ,  Toshihiro Okabe

IPC分类号： H01L27/088 ,  G06F1/04 ,  G06F1/10 ,  G06F15/78 ,  G06F17/50 ,  G11C11/401 ,  H01L21/8234 ,  H03K5/15 ,  H03K19/00 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/096

CPC分类号： G06F1/10 ,  H03K19/00323

摘要： Multi-phase clock signals are delivered to a large number of load circuits scattered on a chip from clock signal input pins through at least three stage buffer circuits. The first stage buffer circuits are arranged in the neighborhood of the input pins, and the second stage buffer circuits are arranged on the central portion of the chip. Equivalent-length wirings are made between the successive two stage buffer circuits and the same number of subsequent stage buffer circuit are connected with each of certain stage buffer circuits for the respective phases so as to provide equal resistances and equal capacitances. Equivalent-length wirings are also made between final stage buffer circuits and the corresponding load circuits, and the same number of load circuits are connected with each final stage buffer circuit. Thus, equal delay times are provided in the clock signal paths from the input pins to the load circuits at the respective phases.

摘要翻译： 多相时钟信号通过至少三级缓冲电路从时钟信号输入引脚传送到分散在芯片上的大量负载电路。 第一级缓冲电路布置在输入引脚附近，第二级缓冲电路布置在芯片的中心部分。 在连续的两级缓冲电路之间进行等效长度布线，并且相同数量的后级缓冲电路与各相的各级缓冲电路连接，以提供相等的电阻和相等的电容。 最终级缓冲电路和相应的负载电路之间也有等长线，并且每个最后级缓冲电路连接相同数量的负载电路。 因此，在从各个相位的输入引脚到负载电路的时钟信号路径中提供相等的延迟时间。

公开(公告)号：US5497263A

公开(公告)日：1996-03-05

申请号：US117525

申请日：1993-09-07

申请人： Noboru Masuda ,  Kazumichi Yamamoto ,  Kazunori Nakajima ,  Toshihiro Okabe ,  Akira Yamagiwa ,  Mikio Yamagishi ,  Kazuo Koide ,  Bunichi Fujita ,  Seiichi Kawashima

发明人： Noboru Masuda ,  Kazumichi Yamamoto ,  Kazunori Nakajima ,  Toshihiro Okabe ,  Akira Yamagiwa ,  Mikio Yamagishi ,  Kazuo Koide ,  Bunichi Fujita ,  Seiichi Kawashima

IPC分类号： G06F1/06 ,  G06F1/10 ,  G11C11/407 ,  G11C11/4076 ,  H03K5/00 ,  H03K5/13 ,  H03K5/131 ,  H03H11/26 ,  H03K17/296

CPC分类号： H03K5/133 ,  G06F1/10 ,  H03K2005/00071 ,  H03K2005/00097 ,  H03K2005/00195

摘要： A variable delay circuit including delay devices each having a plurality of delay units connected successively, only some of the delay units of the delay devices being connected to a signal transmission line, wherein a delay time is controlled by activating or inactivating the plurality of delay units according to control signals applied to control input terminals provided respectively for said plurality of delay units. A clock signal supply device for supplying a second clock signal to a logic circuit block, said clock signal supply device having a clock signal generator for generating a first clock signal and a reference signal and a phase adjusting means for adjusting the phase of the first clock signal phased on a phase difference between the first clock signal and the reference signal and outputting the phase-adjusted signal as a second clock signal, wherein the phase adjusting unit comprises a first variable delay circuit capable of delay operation in initial adjustment of the first clock signal, a second variable delay circuit, disposed in series with the first variable delay circuit, for performing the delay operation after the initial adjustment, and control circuits for controlling delay times of the first and second variable delay circuits.

摘要翻译： 一种可变延迟电路，包括延迟装置，每个延迟装置具有连续连接的多个延迟单元，延迟装置的一些延迟单元连接到信号传输线，其中通过激活或者使多个延迟单元激活来控制延迟时间 根据施加到分别为所述多个延迟单元提供的控制输入端子的控制信号。 一种用于向逻辑电路块提供第二时钟信号的时钟信号提供装置，所述时钟信号提供装置具有用于产生第一时钟信号和参考信号的时钟信号发生器和用于调整第一时钟的相位的相位调整装置 信号相位于第一时钟信号和参考信号之间的相位差，并输出相位调整信号作为第二时钟信号，其中相位调整单元包括能够在第一时钟的初始调整中延迟操作的第一可变延迟电路 信号，与第一可变延迟电路串联布置的第二可变延迟电路，用于在初始调整之后执行延迟操作;以及控制电路，用于控制第一和第二可变延迟电路的延迟时间。

公开(公告)号：US5087829A

公开(公告)日：1992-02-11

申请号：US443503

申请日：1989-12-01

申请人： Kenichi Ishibashi ,  Takehisa Hayashi ,  Toshio Doi ,  Mitsuo Asai ,  Noboru Masuda ,  Akira Yamagiwa ,  Toshihiro Okabe

发明人： Kenichi Ishibashi ,  Takehisa Hayashi ,  Toshio Doi ,  Mitsuo Asai ,  Noboru Masuda ,  Akira Yamagiwa ,  Toshihiro Okabe

IPC分类号： H03K5/15

CPC分类号： H03K5/15

摘要： This invention discloses a clock distribution system which distributes a first clock signal as a reference clock as the reference for the phase and frequency to each processing unit (e.g. LSI) and generates a multi-phase second clock signal to be used in each processing unit by a delay circuit group whose delay time is adjusted. The clock distribution system comprises a clock generation block for generating a one-phase reference clock; a first control loop for comparing the phase of the reference clock with the phase of a feedback signal and adjusting the phase of the reference clock so that their phases are in agreement; and a second control loop including a delay circuit group consisting of a plurality of variable delay circuits to which the reference clock phase-adjusted by the first control loop is inputted and which are connected in series, and means for generating a multi-phase clock signal by use of the output signal of each of the plurality of variable delay circuits and the phase-adjusted referencde clock, controlling the delay time of the plurality of variable delay circuits so as to accomplish a predetermined relation with the period of the phase-adjusted reference clock and applying one of the multi-phase clock signals as the feedback signal described above to the first control loop.

摘要翻译： 本发明公开了一种时钟分配系统，其将作为基准时钟的第一时钟信号作为相位和频率的参考分配给每个处理单元（例如，LSI），并且通过以下方式生成要在每个处理单元中使用的多相第二时钟信号： 延迟时间被调整的延迟电路组。 时钟分配系统包括用于产生单相参考时钟的时钟产生模块; 第一控制环路，用于将参考时钟的相位与反馈信号的相位进行比较，并且调整参考时钟的相位，使得它们的相位一致; 以及包括由多个可变延迟电路组成的延迟电路组的第二控制回路，所述多个可变延迟电路输入由第一控制回路相位调整的参考时钟并串联连接的参考时钟，以及用于产生多相时钟信号的装置 通过使用多个可变延迟电路中的每一个的输出信号和相位调整参考时钟，控制多个可变延迟电路的延迟时间，以便与相位调整参考的周期完成预定的关系 时钟，并将多相时钟信号中的一个作为上述反馈信号施加到第一控制回路。

公开(公告)号：US07046504B2

公开(公告)日：2006-05-16

申请号：US10876622

申请日：2004-06-28

申请人： Atsushi Sakai ,  Ryuji Monden ,  Hiroshi Nitoh ,  Toshihiro Okabe ,  Yuji Furuta ,  Hideki Ohata ,  Koro Shirane

发明人： Atsushi Sakai ,  Ryuji Monden ,  Hiroshi Nitoh ,  Toshihiro Okabe ,  Yuji Furuta ,  Hideki Ohata ,  Koro Shirane

IPC分类号： H01G9/00

CPC分类号： H01G9/15 ,  H01G9/0029 ,  H01G9/04 ,  H01G11/56 ,  Y02E60/13 ,  Y10T29/413 ,  Y10T29/417

摘要： The present invention relates to a solid electrolytic capacitor having a masking structure in which the insulation between the anode part and the cathode part can be ensured without fail, to its production method, to a method for coating a masking agent on a solid electrolytic capacitor substrate, and to apparatus therefore. According to the present invention, the masking material covers the dielectric film on the metal material having valve action and sufficiently infiltrates into the core metal made of a metal having valve action while the solid electrolyte is masked by the masking material without fail, so that a solid electrolytic capacitor can be produced that has a reduced leakage current and a reduced stress generated at the reflow treatment or the like.

摘要翻译： 本发明涉及一种具有掩模结构的固体电解电容器，其中阳极部分和阴极部分之间的绝缘可以毫无保障地确保，其制造方法涉及在固体电解电容器基板上涂覆掩蔽剂的方法 因此，对于设备。 根据本发明，掩模材料覆盖具有阀作用的金属材料上的电介质膜，并且充分渗透到由具有阀作用的金属制成的芯金属中，同时固体电解质被掩蔽材料掩蔽而不会失效， 可以制造具有减小的漏电流和在回流处理等时产生的减小的应力的固体电解电容器。

公开(公告)号：US20060098394A1

公开(公告)日：2006-05-11

申请号：US11311397

申请日：2005-12-20

申请人： Atsushi Sakai ,  Ryuji Monden ,  Hiroshi Nitoh ,  Toshihiro Okabe ,  Yuji Furuta ,  Hideki Ohata ,  Koro Shirane

发明人： Atsushi Sakai ,  Ryuji Monden ,  Hiroshi Nitoh ,  Toshihiro Okabe ,  Yuji Furuta ,  Hideki Ohata ,  Koro Shirane

IPC分类号： H01G9/00

CPC分类号： H01G9/15 ,  H01G9/0029 ,  H01G9/04 ,  H01G11/56 ,  Y02E60/13 ,  Y10T29/413 ,  Y10T29/417

摘要： The present invention relates to a solid electrolytic capacitor having a masking structure in which the insulation between the anode part and the cathode part can be ensured without fail, to its production method, to a method for coating a masking agent on a solid electrolytic capacitor substrate, and to apparatus therefore. According to the present invention, the masking material covers the dielectric film on the metal material having valve action and sufficiently infiltrates into the core metal made of a metal having valve action while the solid electrolyte is masked by the masking material without fail, so that a solid electrolytic capacitor can be produced that has a reduced leakage current and a reduced stress generated at the reflow treatment or the like.

公开(公告)号：US5391900A

公开(公告)日：1995-02-21

申请号：US994056

申请日：1992-12-18

申请人： Yuichi Onodera ,  Toshihiro Okabe ,  Yasuhiro Matsuura ,  Munehiro Sasakawa

发明人： Yuichi Onodera ,  Toshihiro Okabe ,  Yasuhiro Matsuura ,  Munehiro Sasakawa

IPC分类号： H01L21/3205 ,  G06F17/50 ,  H01L21/82 ,  H01L21/822 ,  H01L23/52 ,  H01L23/528 ,  H01L27/04 ,  H01L27/02 ,  H01L27/10

CPC分类号： G06F17/5068 ,  H01L23/528 ,  H01L2924/0002

摘要： The present invention relates to an integrated circuit comprising a semiconductor chip having thereon a logical function portion for realizing logical function and at least one power supply point for supplying electric power to the logical function portion, and at least one first, second and third power trunk line are arranged on the chip for supplying electric power from the power supply point to the logical function portion. The second power trunk line is disposed in an area in which the logical function portion of the chip is disposed. The first power trunk line is disposed between the power supply point and the second power trunk line to connect the second power trunk line with the power supply point. The third trunk line is connected at at least one end to the second trunk line and is disposed in the logical function portion for supplying electric power to the logical function portion.

摘要翻译： 本发明涉及一种集成电路，其包括具有用于实现逻辑功能的逻辑功能部分的半导体芯片和用于向逻辑功能部分提供电力的至少一个电源点，以及至少一个第一，第二和第三电力中继线 线路布置在芯片上，用于从电源点向逻辑功能部分提供电力。 第二电源中继线设置在芯片的逻辑功能部分设置的区域中。 第一电力中继线设置在电源点和第二电力中继线之间，以将第二电力中继线与电源点连接。 第三干线在至少一端连接到第二干线，并且设置在用于向逻辑功能部分供电的逻辑功能部分中。

公开(公告)号：US07617595B2

公开(公告)日：2009-11-17

申请号：US12118242

申请日：2008-05-09

申请人： Hiroshi Nitoh ,  Toshihiro Okabe ,  Kenji Ishii ,  Atsushi Sakai

发明人： Hiroshi Nitoh ,  Toshihiro Okabe ,  Kenji Ishii ,  Atsushi Sakai

IPC分类号： B23P19/00

CPC分类号： H01G13/00 ,  Y10T29/49121 ,  Y10T29/5313 ,  Y10T29/53183 ,  Y10T29/53187 ,  Y10T29/532 ,  Y10T29/53213 ,  Y10T29/53217

摘要： The present invention relates to an apparatus for producing a comb-like capacitor element member including a guide member and a plurality of rectangular metal foil pieces bonded to the guide member, comprising an automatic feed mechanism for feeding tape-like metal foil by a constant length toward the guide member, a bonding mechanism for bonding the metal foil to the guide member, and a cutting mechanism for cutting the bonded metal foil. According to the apparatus of the present invention, a comb-like capacitor element member having a plurality of rectangular metal foil pieces bonded can be produced efficiently, by bonding the elongated tape-like metal foil without damaging it.

摘要翻译： 本发明涉及一种用于制造梳状电容器元件的装置，该梳状电容器元件包括引导件和多个矩形金属箔片接合到导向件上，该自动进给机构用于将带状金属箔以恒定的长度 朝向引导构件，用于将金属箔接合到引导构件的接合机构，以及用于切割接合的金属箔的切割机构。 根据本发明的装置，可以有效地制造具有多个矩形金属箔片的梳状电容器元件，通过将细长的带状金属箔粘合而不会损坏。

公开(公告)号：US06890363B1

公开(公告)日：2005-05-10

申请号：US09576957

申请日：2000-05-24

申请人： Atsushi Sakai ,  Ryuji Monden ,  Hiroshi Nitoh ,  Toshihiro Okabe ,  Yuji Furuta ,  Hideki Ohata ,  Koro Shirane

发明人： Atsushi Sakai ,  Ryuji Monden ,  Hiroshi Nitoh ,  Toshihiro Okabe ,  Yuji Furuta ,  Hideki Ohata ,  Koro Shirane

IPC分类号： H01G9/00 ,  H01G9/04 ,  H01G9/15 ,  H01L21/00

CPC分类号： H01G9/15 ,  H01G9/0029 ,  H01G9/04 ,  H01G11/56 ,  Y02E60/13 ,  Y10T29/413 ,  Y10T29/417

摘要： The present invention relates to a solid electrolytic capacitor having a masking structure in which the insulation between the anode part and the cathode part can be ensured without fail, to its production method, to a method for coating a masking agent on a solid electrolytic capacitor substrate, and to an apparatus therefor. According to the present invention, the masking material covers the dielectric film on the metal material having valve action and sufficiently infiltrates into the core metal made of a metal having valve action while the solid electrolyte is masked by the masking material without fail, so that a solid electrolytic capacitor can be produced that has a reduced leakage current and a reduced stress generated at the reflow treatment or the like.

摘要翻译： 本发明涉及一种具有掩模结构的固体电解电容器，其中阳极部分和阴极部分之间的绝缘可以毫无保障地确保，其制造方法涉及在固体电解电容器基板上涂覆掩蔽剂的方法 ，以及其设备。 根据本发明，掩模材料覆盖具有阀作用的金属材料上的电介质膜，并且充分渗透到由具有阀作用的金属制成的芯金属中，同时固体电解质被掩蔽材料掩蔽而不会失效， 可以制造具有减小的漏电流和在回流处理等时产生的减小的应力的固体电解电容器。