公开(公告)号：US5852318A

公开(公告)日：1998-12-22

申请号：US25998

申请日：1998-02-19

申请人： Kiyoshi Chikamatsu ,  Toshiro Watanabe ,  Toshiaki Inoue ,  Yasushi Kose

发明人： Kiyoshi Chikamatsu ,  Toshiro Watanabe ,  Toshiaki Inoue ,  Yasushi Kose

IPC分类号： H01L29/78 ,  H01L29/417 ,  H01L29/423 ,  H01L29/80 ,  H01L29/76 ,  H01L23/62

CPC分类号： H01L29/7835 ,  H01L29/4175 ,  H01L29/41758 ,  H01L29/4238 ,  H01L2924/0002

摘要： A semiconductor device includes: a plurality of first field effect transistors (FETs) having a gate formed on a main surface of a semiconductor substrate, and a drain and a source formed in regions on both sides of the gate; a plurality of second FETs having a gate formed on the main surface of the semiconductor substrate, and a drain and a source formed in regions on both sides of the gate; and an electrically conductive layer that penetrates the main surface and a back surface of the semiconductor substrate in a region between the pair of FETs; wherein the first and second FETs that form the pair of FETs are disposed close to each other so that their drains are opposite to each other; wherein region widths of the first and second FETs in a direction of shorter sides of sources thereof are substantially identical with region widths of the first and second FETs in a direction of shorter sides of drains thereof; wherein all the drains of the first and second FETs are electrically connected to each other; wherein all the gates of the first and second FETs are electrically connected to each other; and wherein all the sources of the first and second FETs are electrically connected to each other on the back surface of the semiconductor substrate through the conductive layer.

摘要翻译： 半导体器件包括：多个第一场效应晶体管（FET），其具有形成在半导体衬底的主表面上的栅极，以及漏极和源极，形成在栅极两侧的区域中; 多个第二FET，其具有形成在半导体衬底的主表面上的栅极，以及形成在栅极两侧的区域中的漏极和源极; 以及在所述一对FET之间的区域中穿透所述半导体衬底的主表面和后表面的导电层; 其中形成所述一对FET的所述第一和第二FET彼此靠近设置，使得它们的漏极彼此相对; 其中，所述第一FET和所述第二FET的源极的短边方向的区域宽度与所述第一和第二FET的漏极的短边方向的区域宽度基本相同; 其中所述第一和第二FET的所有漏极彼此电连接; 其中所述第一和第二FET的所有栅极彼此电连接; 并且其中所述第一和第二FET的所有源极通过所述导电层在所述半导体衬底的背表面上彼此电连接。

公开(公告)号：USRE32985E

公开(公告)日：1989-07-11

申请号：US906848

申请日：1986-09-15

申请人： Masanori Nagata ,  Toshiaki Inoue ,  Mamoru Hirayama

发明人： Masanori Nagata ,  Toshiaki Inoue ,  Mamoru Hirayama

IPC分类号： G07F7/08 ,  G07F19/00

CPC分类号： G07F7/08 ,  G06Q20/4037 ,  G07F19/20 ,  G07F19/201

摘要： A credit transaction processing system processes data related to a commodity entered into by using a card (17) owned by a customer and a recording card (16) owned by a store. First, merchant transaction data necessary for a credit sale stored in the recording medium (16), such as account number data for the store, data specifying a credit company, and data representing an upper limit of an amount to to be sold through a credit sale, are read by a card reader (5), and then, customer transaction data stored in the customer's recording card, such as account number data of the customer, data specifying a credit company and an identification number or code is read. If and when the customer enters his identification number by a ten-key (7), a central processing unit (12) determines whether the entered identification number coincides with the identification number read out of the customer's card. If and when a coincidence occurs, it is determined whether data indicating the purchase price of the commodity purchased by the customer is lower than the upper limit of the amount to be sold through a credit sale. If so, the price data is transmitted to a center station (3) and the amount of the money required for the credit sale is transferred from the bank account of the credit company utilized by the customer to the bank account of the store.

公开(公告)号：US4594663A

公开(公告)日：1986-06-10

申请号：US512022

申请日：1983-07-08

申请人： Masanori Nagata ,  Toshiaki Inoue ,  Mamoru Hirayama

发明人： Masanori Nagata ,  Toshiaki Inoue ,  Mamoru Hirayama

IPC分类号： G06Q20/40 ,  G06Q20/00 ,  G06Q20/24 ,  G06Q20/42 ,  G06Q40/00 ,  G06Q40/02 ,  G06Q50/00 ,  G06Q50/26 ,  G07F7/08 ,  G07F19/00 ,  G06F15/30

CPC分类号： G07F7/08 ,  G06Q20/105 ,  G06Q20/202 ,  G06Q20/204 ,  G06Q20/40 ,  G06Q20/4037 ,  G07F19/20 ,  G07F19/201

摘要： A credit transaction processing system processes data related to a commodity entered into by using a card (17) owned by a customer and a recording card (16) owned by a store. First, merchant transaction data necessary for a credit sale stored in the recording medium (16), such as account number data for the store, data specifying a credit company, and data representing an upper limit of an amount to to be sold through a credit sale, are read by a card reader (5), and then, customer transaction data stored in the customer's recording card, such as account number data of the customer, data specifying a credit company and an identification number or code is read. If and when the customer enters his identification number by a ten-key (7), a central processing unit (12) determines whether the entered identification number coincides with the identification number read out of the customer's card. If and when a coincidence occurs, it is determined whether data indicating the purchase price of the commodity purchased by the customer is lower than the upper limit of the amount to be sold through a credit sale. If so, the price data is transmitted to a center station (3) and the amount of the money required for the credit sale is transferred from the bank account of the credit company utilized by the customer to the bank account of the store.

摘要翻译： 信用交易处理系统通过使用客户拥有的卡（17）和由商店拥有的记录卡（16）来处理与进入的商品有关的数据。 首先，存储在记录介质（16）中的信用销售所需的商家交易数据，例如商店的帐号数据，指定信用公司的数据，以及表示通过信用销售的金额的上限的数据 销售，由读卡器（5）读取，然后读取存储在客户记录卡中的客户交易数据，例如客户的帐号数据，指定信用公司的数据和识别号码或代码。 如果客户通过十键（7）输入其识别号码，则中央处理单元（12）确定输入的识别号码是否与从客户卡片读出的识别号码一致。 如果发生巧合，则确定表示客户购买的商品的购买价格的数据是否低于通过信用销售出售的金额的上限。 如果是这样，将价格数据传送到中心站（3），信用销售所需的金额从客户利用的信用公司的银行账户转入商店的银行账户。

公开(公告)号：US20080027626A1

公开(公告)日：2008-01-31

申请号：US11879605

申请日：2007-07-18

申请人： Toshiaki Inoue

发明人： Toshiaki Inoue

IPC分类号： F02D41/00

CPC分类号： F02D41/0235 ,  F02D41/1446

摘要： Fuel efficient devices and methods for protecting an exhaust system, and components thereof, when the exhaust gas temperature increases excessively are provided. The exhaust gas temperature is estimated in response to an internal resistance of an Air/Fuel ratio sensor element. The estimated temperature is corrected in a transition time based on the exhaust gas flow rate and the engine's operating region. When the exhaust gas temperature reaches an upper limit (Tmax), a delay period is set in response to the change ratio of the exhaust gas temperature. The delay period is based on the margin of time before an exhaust system component reaches the allowable heat resistance temperature Tem. The delay period can be corrected based on the outside air temperature and the vehicle speed. After the delay time has elapsed, a fuel increment is started in order to decrease the exhaust temperature.

摘要翻译： 提供了当废气温度过高时用于保护排气系统及其部件的燃料效率的装置和方法。 废气温度是根据空气/燃料比传感器元件的内部电阻来估计的。 基于废气流量和发动机的工作区域，在过渡时间内校正估计温度。 当废气温度达到上限（Tmax）时，响应于废气温度的变化比设定延迟时间。 延迟时间基于排气系统组件达到允许耐热温度Tem之前的余量。 可以基于外部空气温度和车辆速度来校正延迟时间。 在延迟时间过去之后，为了降低排气温度，启动燃料增量。

公开(公告)号：US20070176911A1

公开(公告)日：2007-08-02

申请号：US10563748

申请日：2004-07-08

申请人： Toshiaki Inoue

发明人： Toshiaki Inoue

IPC分类号： G06F3/038

CPC分类号： H04L25/0282

摘要： A data transfer circuit comprises a voltage/current converter circuit for converting a first binary voltage data of n bits (n is an integer equal to or larger than two) to multi-value current data of 2n values which is output to a single data transfer line. A current comparator circuit converts the multi-value current data on the data transfer line to binary current data of (2n−1) bits, and a current/voltage converter circuit converts the binary current data of the (2n−1) bits to second binary voltage data of (2n−1) bits. A counter circuit restores the first binary voltage data of the n bits from the second binary voltage data of the (2n−1) bits.

摘要翻译： 数据传输电路包括电压/电流转换器电路，用于将n位（n是等于或大于2的整数）的第一二进制电压数据转换为2值的多值电流数据 其被输出到单个数据传输线。 电流比较器电路将数据传输线上的多值电流数据转换为（2 1）比特的二进制电流数据，并且电流/电压转换器电路将二进制电流数据 （2 1）位的第二二进制电压数据。 计数器电路从第（2n-n-1）位的第二二进制电压数据恢复n位的第一二进制电压数据。

公开(公告)号：US06243083B1

公开(公告)日：2001-06-05

申请号：US09119623

申请日：1998-07-21

申请人： Akira Arimizu ,  Shozo Mitarai ,  Toshiaki Inoue

发明人： Akira Arimizu ,  Shozo Mitarai ,  Toshiaki Inoue

IPC分类号： G09G500

CPC分类号： H04N9/646 ,  H04N5/208

摘要： To obtain a clear-cut picture image by correcting a contour of a video signal of a natural picture image and the like from a computer. Video signals of, for example, three primary colors (R, G, B), including a natural picture image and the like produced by, for example, a computer from input terminals 1 are supplied to a mixing circuit (2) and mixed at a ratio of, for example, 0.6G+0.3R+0.1B to produce a signal corresponding to a luminance (Y). This signal is supplied to differentiation circuits 3A and 3B having different time constants each other and predetermined high frequency components are extracted therefrom, respectively, and these output signals are selected by a switch (4), and then supplied to an amplifying circuit 5. The gain of the amplifying circuit 5 is arbitrarily controlled by a signal from a control terminal (6). Then, a signal from the amplifying circuit (5) is supplied to adding circuits 7R, 7G and 7B and added therein to respective video signals of R, G and B to then be derived from output terminals 8R, 8G and 8B.

摘要翻译： 通过从计算机校正自然图像图像等的视频信号的轮廓来获得清晰的图像图像。例如，包括自然图像的三原色（R，G，B）的视频信号 由例如来自输入端子1的计算机产生的图像等被提供给混合电路（2），并以例如0.6G + 0.3R + 0.1B的比率混合，以产生对应于 亮度（Y）。 该信号被提供给具有不同时间常数的微分电路3A和3B，并且分别从其中提取预定的高频分量，并且这些输出信号由开关（4）选择，然后提供给放大电路5。 放大电路5的增益由来自控制端子（6）的信号任意地控制。 然后，将来自放大电路（5）的信号提供给加法电路7R，7G和7B，并将其加到相应的R，G和B的视频信号中，然后从输出端子8R，8G和8B导出。

公开(公告)号：US06219777B1

公开(公告)日：2001-04-17

申请号：US09113291

申请日：1998-07-10

申请人： Toshiaki Inoue

发明人： Toshiaki Inoue

IPC分类号： G06F1500

CPC分类号： G06F9/3012 ,  G06F9/30141 ,  G06F9/3885

摘要： Disclosed is a register file used in a multiprocessor composition composed of a plurality of processor elements, the register file having a plurality of words and being provided for each of the plurality of processor elements, wherein: the plurality of words are divided into a word part that can be simultaneously accessed by some of the plurality of processor elements to use in common with other processor element, and a word part that can be accessed only by its own processor element.

摘要翻译： 公开了一种用于由多个处理器元件组成的多处理器组合中的寄存器文件，该寄存器文件具有多个单词并且为多个处理器单元中的每一个提供，其中：多个单词被分成单词部分 可以由多个处理器元件中的一些同时访问以与其他处理器元件共同使用的单词部分，以及只能由其自己的处理器元件访问的单词部分。

公开(公告)号：US4674620A

公开(公告)日：1987-06-23

申请号：US715452

申请日：1985-03-25

申请人： Toshiaki Inoue

发明人： Toshiaki Inoue

IPC分类号： B23Q7/00 ,  B23Q7/14 ,  B65G47/00

CPC分类号： B23Q7/1452 ,  B23Q7/005

摘要： An apparatus and a method of positioning pallets on roller chains mounted on a free flow conveyor is basically composed of a detector for detecting an oncoming pallet, a stopper for stopping the pallet at an approximately required position, a controller capable of positioning the pallet in the x- and y-directions, and another controller capable of positioning the pallet in the z-direction. With an application of the foregoing method proposed, a device is designed to provide a highly accurate positioning of the pallet with a single device and therefore contributes greatly to an economization of operating costs.

摘要翻译： 将托盘定位在安装在自由流动输送机上的滚子链上的装置和方法基本上由用于检测迎面而来的托盘的检测器，用于在大约所需位置停止托盘的止动器，能够将托盘定位在托盘中的控制器 x方向和y方向，以及能够将托盘定位在z方向上的另一控制器。 通过提出上述方法的应用，设备被设计成通过单个装置提供托盘的高精度定位，因此有助于节省运行成本。

公开(公告)号：US07508241B2

公开(公告)日：2009-03-24

申请号：US10563748

申请日：2004-07-08

申请人： Toshiaki Inoue

发明人： Toshiaki Inoue

IPC分类号： H02M11/00

CPC分类号： H04L25/0282

摘要： A data transfer circuit comprises a voltage/current converter circuit for converting a first binary voltage data of n bits (n is an integer equal to or larger than two) to multi-value current data of 2n values which is output to a single data transfer line. A current comparator circuit converts the multi-value current data on the data transfer line to binary current data of (2n−1) bits, and a current/voltage converter circuit converts the binary current data of the (2n−1) bits to second binary voltage data of (2n−1) bits. A counter circuit restores the first binary voltage data of the n bits from the second binary voltage data of the (2n−1) bits.

公开(公告)号：US5933362A

公开(公告)日：1999-08-03

申请号：US797121

申请日：1997-02-10

申请人： Toshiaki Inoue

发明人： Toshiaki Inoue

IPC分类号： G06F7/501 ,  G06F7/50 ,  G06F7/503 ,  G06F7/506 ,  G06F7/508 ,  G06F7/38

CPC分类号： G06F7/508

摘要： An adder has a carry signal generation block for producing carry generation signal bits representative of carry bits resulted from augend signal bits and addend signal bits and carry propagation signal bits representative of carry bits resulted from the augend signal bits, the addend signal bits and the carry bits supplied from lower-digits, a carry propagation block responsive to control signal bits for dividing the adder into partial adders and having propagation stages for producing carry signal bits from the carry generation signal bits, the carry propagation signal bits and the control signal bits, and a sum generation block for producing sum signal bits from the carry propagation signal bits, the control signal bits and the carry signal bits, and is divisible into an arbitrary number of partial adders without increase the stages of a critical path.

摘要翻译： 加法器具有进位信号生成块，用于产生表示由加法信号位和加数信号位产生的进位位的进位产生信号位，并携带表示由加法信号位，加数信号位和进位产生的进位位的传播信号位 从低位数字提供的位，响应于控制信号位的进位传播块，用于将加法器分成部分加法器，并具有用于从进位产生信号位，进位传播信号位和控制信号位产生进位信号位的传播级， 以及用于从进位传播信号位，控制信号位和进位信号位产生和信号位的和产生块，并且可以在不增加关键路径的级的情况下被划分为任意数量的部分加法器。