公开(公告)号：US20130093003A1

公开(公告)日：2013-04-18

申请号：US13607255

申请日：2012-09-07

申请人： Hiroyuki IRIFUNE ,  Wataru SAITO ,  Yasuto SUMI ,  Kiyoshi KIMURA ,  Hiroshi OHTA ,  Junji SUZUKI

发明人： Hiroyuki IRIFUNE ,  Wataru SAITO ,  Yasuto SUMI ,  Kiyoshi KIMURA ,  Hiroshi OHTA ,  Junji SUZUKI

IPC分类号： H01L29/78

CPC分类号： H01L29/7802 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/7811

摘要： A semiconductor device includes first, second, and third semiconductor layers each having multiple diffusion layers. The first direction widths of the first diffusion layers are the same. The amount of impurity within the first diffusion layers gradually increases from the bottom end towards the top end of the first semiconductor layer. The first direction widths of the second diffusion layers are the same. The amounts of impurity within the second diffusion layers are the same. The first direction widths of the third diffusion layers are narrower than the first direction widths of the first diffusion layers and the first direction widths of the second diffusion layers at the same level, and gradually become narrower from the bottom end towards the top end of the third semiconductor layer. The amount of impurity within the third. diffusion layers are the same.

摘要翻译： 半导体器件包括各自具有多个扩散层的第一，第二和第三半导体层。 第一扩散层的第一方向宽度相同。 第一扩散层内的杂质量从第一半导体层的底端向顶端逐渐增加。 第二扩散层的第一方向宽度相同。 第二扩散层内的杂质量相同。 第三扩散层的第一方向宽度比第一扩散层的第一方向宽度和第二扩散层的第一方向宽度在相同水平处窄，并且从第一扩散层的第一方向宽度逐渐变窄到 第三半导体层。 第三者内的杂质量。 扩散层是相同的。

公开(公告)号：US20120074491A1

公开(公告)日：2012-03-29

申请号：US13234802

申请日：2011-09-16

申请人： Hiroshi OHTA ,  Yasuto SUMI ,  Kiyoshi KIMURA ,  Junji SUZUKI ,  Hiroyuki IRIFUNE ,  Wataru SAITO ,  Syotaro ONO

发明人： Hiroshi OHTA ,  Yasuto SUMI ,  Kiyoshi KIMURA ,  Junji SUZUKI ,  Hiroyuki IRIFUNE ,  Wataru SAITO ,  Syotaro ONO

IPC分类号： H01L27/088

CPC分类号： H01L29/78 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/42356 ,  H01L29/42372 ,  H01L29/7811 ,  H01L29/7813

摘要： In general, according to one embodiment, a power semiconductor device includes a first pillar region, a second pillar region, and an epitaxial layer of a first conductivity type on a first semiconductor layer. The first pillar region is composed of a plurality of first pillar layers of a second conductivity type and a plurality of second pillar layers of the first conductivity type alternately arranged along a first direction. The second pillar region is adjacent to the first pillar region along the first direction and includes a third pillar layer of the second conductivity type, a fourth pillar layer of the first conductivity type, and a fifth pillar layer of the second conductivity type in this order along the first direction. A plurality of second base layers of the second conductivity type electrically connected, respectively, onto the third pillar layer and the fifth pillar layer and spaced from each other.

摘要翻译： 通常，根据一个实施例，功率半导体器件包括在第一半导体层上的第一导电类型的第一柱状区域，第二柱状区域和外延层。 第一支柱区域由第一导电类型的多个第一支柱层和沿第一方向交替布置的第一导电类型的多个第二支柱层组成。 第二柱状区域沿着第一方向与第一柱状区域相邻，并且具有第二导电型的第三柱状层，第一导电型的第四柱状层和第二导电型的第五柱状层 沿着第一个方向。 多个第二导电类型的第二基极层分别电连接到第三柱层和第五柱层上并彼此间隔开。

公开(公告)号：US20130069158A1

公开(公告)日：2013-03-21

申请号：US13425258

申请日：2012-03-20

申请人： Hiroshi OHTA ,  Yasuto Sumi ,  Kiyoshi Kimura ,  Junji Suzuki ,  Hiroyuki Irifune ,  Wataru Saito

发明人： Hiroshi OHTA ,  Yasuto Sumi ,  Kiyoshi Kimura ,  Junji Suzuki ,  Hiroyuki Irifune ,  Wataru Saito

IPC分类号： H01L29/78

CPC分类号： H01L29/0623 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7811

摘要： A power semiconductor device includes a high resistance epitaxial layer having a first pillar region and a second pillar region as a drift layer. The first pillar region includes a plurality of first pillars of the first conductivity type and a plurality of second pillars of the second conductivity type disposed alternately along a first direction. The second pillar region is adjacent to the first pillar region along the first direction. The second pillar region includes a third pillar and a fourth pillar of a conductivity type opposite to a conductivity type of the third pillar. A net quantity of impurities in the third pillar is less than a net quantity of impurities in each of the plurality of first pillars. A net quantity of impurities in the fourth pillar is less than the net quantity of impurities in the third pillar.

摘要翻译： 功率半导体器件包括具有第一柱区和第二柱区作为漂移层的高电阻外延层。 第一支柱区域包括多个第一导电类型的第一支柱和沿着第一方向交替布置的多个第二导电类型的第二支柱。 第二柱区域沿着第一方向与第一柱状区域相邻。 第二柱区域包括与第三柱的导电类型相反的导电类型的第三柱和第四柱。 第三支柱中的杂质净量少于多个第一支柱中的每一个中的杂质的净量。 第四柱中净杂质量少于第三柱中杂质的净量。

公开(公告)号：US20120061721A1

公开(公告)日：2012-03-15

申请号：US13229203

申请日：2011-09-09

申请人： Kiyoshi KIMURA ,  Yasuto SUMI ,  Hiroshi OHTA ,  Hiroyuki IRIFUNE

发明人： Kiyoshi KIMURA ,  Yasuto SUMI ,  Hiroshi OHTA ,  Hiroyuki IRIFUNE

IPC分类号： H01L27/082 ,  H01L21/331

CPC分类号： H01L29/0634 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/872

摘要： A power semiconductor device includes a first semiconductor layer of a first conductivity type, a first drift layer, and a second drift layer. The first drift layer includes a first epitaxial layer of the first conductivity type, a plurality of first first-conductivity-type pillar layers, and a plurality of first second-conductivity-type pillar layers. The second drift layer is formed on the first drift layer and includes a second epitaxial layer of the first conductivity type, a plurality of second second-conductivity-type pillar layers, a plurality of second first-conductivity-type pillar layers, a plurality of third second-conductivity-type pillar layers, and a plurality of third first-conductivity-type pillar layers. The plurality of second second-conductivity-type pillar layers are connected to the first second-conductivity-type pillar layers. The plurality of second first-conductivity-type pillar layers are connected to the first first-conductivity-type pillar layers. The plurality of third second-conductivity-type pillar layers are arranged on the first epitaxial layer.

摘要翻译： 功率半导体器件包括第一导电类型的第一半导体层，第一漂移层和第二漂移层。 第一漂移层包括第一导电类型的第一外延层，多个第一第一导电型柱层和多个第一第二导电型柱层。 第二漂移层形成在第一漂移层上，并且包括第一导电类型的第二外延层，多个第二第二导电型柱层，多个第二第一导电型柱层，多个第二导电型柱层 第三第二导电型柱层和多个第三第一导电型柱层。 多个第二第二导电型柱层与第一第二导电型柱层连接。 多个第二第一导电型柱层与第一第一导电型柱层连接。 多个第三第二导电型柱层布置在第一外延层上。

公开(公告)号：US20110018055A1

公开(公告)日：2011-01-27

申请号：US12840201

申请日：2010-07-20

申请人： Hiroshi OHTA ,  Yasuto SUMI ,  Kiyoshi KIMURA ,  Wataru SEKINE ,  Wataru SAITO ,  Syotaro ONO ,  Munehisa YABUZAKI ,  Nana HATANO ,  Miho WATANABE

发明人： Hiroshi OHTA ,  Yasuto SUMI ,  Kiyoshi KIMURA ,  Wataru SEKINE ,  Wataru SAITO ,  Syotaro ONO ,  Munehisa YABUZAKI ,  Nana HATANO ,  Miho WATANABE

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66712 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/7811

摘要： According to one embodiment, a power semiconductor device includes a first semiconductor layer, and first, second and third semiconductor regions. The first semiconductor layer has a first conductivity type. The first semiconductor regions have a second conductivity type, and are formed with periodicity in a lateral direction in a second semiconductor layer of the first conductivity type. The second semiconductor layer is provided on a major surface of the first semiconductor layer in a device portion with a main current path formed in a vertical direction generally perpendicular to the major surface and in a terminal portion provided around the device portion. The second semiconductor region has the first conductivity type and is a portion of the second semiconductor layer sandwiched between adjacent ones of the first semiconductor regions. The third semiconductor regions have the second conductivity type and are provided below the first semiconductor regions in the terminal portion.

摘要翻译： 根据一个实施例，功率半导体器件包括第一半导体层以及第一，第二和第三半导体区域。 第一半导体层具有第一导电类型。 第一半导体区域具有第二导电类型，并且在第一导电类型的第二半导体层中在横向方向上形成周期性。 第二半导体层设置在器件部分的第一半导体层的主表面上，其主电流通道形成在大体上垂直于主表面的垂直方向上，以及设置在器件部分周围的端子部分中。 第二半导体区域具有第一导电类型，并且是夹在相邻的第一半导体区域中的第二半导体层的一部分。 第三半导体区域具有第二导电类型并且设置在端子部分中的第一半导体区域的下方。

公开(公告)号：US20100038712A1

公开(公告)日：2010-02-18

申请号：US12540192

申请日：2009-08-12

申请人： Miho WATANABE ,  Masaru IZUMISAWA ,  Yasuto SUMI ,  Hiroshi OHTA ,  Wataru SEKINE ,  Wataru SAITO ,  Syotaro ONO ,  Nana HATANO

发明人： Miho WATANABE ,  Masaru IZUMISAWA ,  Yasuto SUMI ,  Hiroshi OHTA ,  Wataru SEKINE ,  Wataru SAITO ,  Syotaro ONO ,  Nana HATANO

IPC分类号： H01L29/78

CPC分类号： H01L29/7811 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/7802

摘要： A semiconductor device according to an embodiment of the present invention includes a device part and a terminal part. The device includes a first semiconductor layer, and second and third semiconductor layers formed on the first semiconductor layer, and alternately arranged along a direction parallel to a surface of the first semiconductor layer, wherein the device part is provided with a first region and a second region, each of which includes at least one of the second semiconductor layers and at least one of the third semiconductor layers, and with regard to a difference value ΔN (=NA−NB) obtained by subtracting an impurity amount NB per unit length of each of the third semiconductor layers from an impurity amount NA per unit length of each of the second semiconductor layers, a difference value ΔNC1 which is the difference value ΔN in the first region of the device part, a difference value ΔNC2 which is the difference value ΔN in the second region of the device part, and a difference value ΔNT which is the difference value ΔN in the terminal part satisfy a relationship of ΔNC1>ΔNT>ΔNC2.

摘要翻译： 根据本发明实施例的半导体器件包括器件部分和端子部分。 该器件包括第一半导体层，以及形成在第一半导体层上的第二和第三半导体层，并且沿着与第一半导体层的表面平行的方向交替布置，其中器件部分设置有第一区域和第二半导体层 区域，其中每一个包括第二半导体层和至少一个第三半导体层中的至少一个，并且关于通过从每单位长度减去杂质量NB获得的差值Dgr; N（= NA-NB） 从每个第二半导体层的每单位长度的杂质量NA中的每个第三半导体层的差分值＆Dgr; NC1，其是器件部分的第一区域中的差值＆Dgr; N，差值＆Dgr ;作为装置部分的第二区域中的差值Dgr; N的NC2，作为终端部分中的差值Dgr; N的差值＆Dgr; NT满足关系 的＆Dgr; NC1>＆Dgr; NT>＆Dgr; NC2。

公开(公告)号：US20080315297A1

公开(公告)日：2008-12-25

申请号：US12144985

申请日：2008-06-24

申请人： Masakatsu TAKASHITA ,  Yasuto SUMI ,  Masaru IZUMISAWA ,  Hiroshi OHTA ,  Wataru SAITO ,  Syotaro ONO

发明人： Masakatsu TAKASHITA ,  Yasuto SUMI ,  Masaru IZUMISAWA ,  Hiroshi OHTA ,  Wataru SAITO ,  Syotaro ONO

IPC分类号： H01L29/78

CPC分类号： H01L21/26513 ,  H01L21/26586 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/32 ,  H01L29/402 ,  H01L29/66712 ,  H01L29/7811

摘要： There is provided a semiconductor device having a drift layer with a pillar structure including first semiconductor layer portions of the first conduction type and second semiconductor layer portions of the second conduction type formed in pillars alternately and periodically on a semiconductor substrate. A device region includes a plurality of arrayed transistors composed of the first semiconductor layer portions and the second semiconductor layer portions. A terminal region is formed at the periphery of the device region without the transistors formed therein. The drift layer in the terminal region has a carrier lifetime lower than ⅕ the carrier lifetime in the drift layer in the device region.

摘要翻译： 提供一种具有柱状结构的漂移层的半导体器件，其包括第一导电类型的第一半导体层部分和第二导电类型的第二半导体层部分在半导体衬底上交替周期地形成为柱状。 器件区域包括由第一半导体层部分和第二半导体层部分组成的多个阵列晶体管。 端子区域形成在器件区域的外围，而不形成晶体管。 端子区域中的漂移层的载流子寿命低于器件区域漂移层中的载流子寿命的1/5。

公开(公告)号：US20110233656A1

公开(公告)日：2011-09-29

申请号：US13049634

申请日：2011-03-16

申请人： Hiroshi OHTA ,  Yasuto Sumi ,  Klyoshi Kimura

发明人： Hiroshi OHTA ,  Yasuto Sumi ,  Klyoshi Kimura

IPC分类号： H01L29/78 ,  H01L21/425

CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/66712

摘要： According to one embodiment, a semiconductor device includes a semiconductor layer of a first conductivity type, first semiconductor pillar regions of the first conductivity type and second semiconductor pillar regions of a second conductivity type, a semiconductor region of the first conductivity type, a base region of the second conductivity type, a source region, a first main electrode, a second main electrode and a control electrode. The second semiconductor pillar region includes a plurality of semiconductor regions of the second conductivity type. A difference is provided between peak values of impurity concentration profiles of an uppermost and a lowermost semiconductor regions of the plurality of semiconductor regions, and in the alternately arranging direction of the first and second semiconductor pillar regions, maximum width of the uppermost semiconductor region is generally equal to or narrower than maximum width of the lowermost semiconductor region.

摘要翻译： 根据一个实施例，半导体器件包括第一导电类型的半导体层，第一导电类型的第一半导体柱区域和第二导电类型的第二半导体柱区域，第一导电类型的半导体区域，基极区域 的第二导电类型，源极区，第一主电极，第二主电极和控制电极。 第二半导体柱区域包括第二导电类型的多个半导体区域。 在多个半导体区域的最上半导体区域和最下半导体区域的杂质浓度分布的峰值之间，在第一和第二半导体柱区域的交替排列方向上，最上半导体区域的最大宽度一般是 等于或窄于最低半导体区域的最大宽度。

公开(公告)号：US20090236697A1

公开(公告)日：2009-09-24

申请号：US12403881

申请日：2009-03-13

申请人： Syotaro ONO ,  Wataru SAITO ,  Nana HATANO ,  Masaru IZUMISAWA ,  Yasuto SUMI ,  Hiroshi OHTA ,  Wataru SEKINE ,  Miho WATANABE

发明人： Syotaro ONO ,  Wataru SAITO ,  Nana HATANO ,  Masaru IZUMISAWA ,  Yasuto SUMI ,  Hiroshi OHTA ,  Wataru SEKINE ,  Miho WATANABE

IPC分类号： H01L29/06 ,  H01L21/20

CPC分类号： H01L29/66712 ,  H01L21/266 ,  H01L29/0615 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/7395 ,  H01L29/7811

摘要： A semiconductor device includes a super junction region that has a first-conductivity-type first semiconductor pillar region and a second-conductivity-type second semiconductor pillar region alternately provided on the semiconductor substrate. The first semiconductor pillar region and the second semiconductor pillar region in a termination region have a lamination form resulting from alternate lamination of the first semiconductor pillar region and the second semiconductor pillar region on the top surface of the semiconductor substrate. The first semiconductor pillar region and/or the second semiconductor pillar region at a corner part of the termination region exhibit an impurity concentration distribution such that a plurality of impurity concentration peaks appear periodically. The first semiconductor pillar region and/or the second semiconductor pillar region at a corner part of the termination region have an impurity amount such that it becomes smaller as being closer to the circumference of the corner part.

摘要翻译： 半导体器件包括具有交替设置在半导体衬底上的第一导电型第一半导体柱区域和第二导电型第二半导体柱区域的超结区域。 终端区域中的第一半导体柱区域和第二半导体柱区域具有由半导体衬底的顶表面上的第一半导体柱区域和第二半导体柱区域的交替层叠形成的叠层形式。 终端区域的角部处的第一半导体柱区域和/或第二半导体柱区域显示杂质浓度分布，使得多个杂质浓度峰值周期性出现。 终端区域的角部处的第一半导体柱区域和/或第二半导体柱区域具有使得随着角部更靠近圆周而变小的杂质量。

公开(公告)号：US20100264489A1

公开(公告)日：2010-10-21

申请号：US12719475

申请日：2010-03-08

申请人： Hiroshi OHTA ,  Wataru SAITO ,  Syotaro ONO ,  Munehisa YABUZAKI ,  Nana HATANO ,  Miho WATANABE

发明人： Hiroshi OHTA ,  Wataru SAITO ,  Syotaro ONO ,  Munehisa YABUZAKI ,  Nana HATANO ,  Miho WATANABE

IPC分类号： H01L27/06 ,  H01L29/78

CPC分类号： H01L29/7811 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/7395 ,  H01L29/7813

摘要： A transistor contains a first semiconductor layer of a first conductivity type and a drift layer having a pillar structure in which a second semiconductor layer of the first conductivity type and a third semiconductor layer of a second conductivity type are alternately disposed in a direction parallel to a surface of the first semiconductor layer. The fourth semiconductor layer of the first conductivity type and the fifth semiconductor layer of the second conductivity type are alternately disposed and parallel to the drift layer. The fifth semiconductor layer has a larger amount of impurities than the fourth semiconductor layer. The sixth semiconductor layer of the first conductivity type and the seventh semiconductor layer of the second conductivity type are alternately disposed and parallel to the fourth and the fifth semiconductor layers. The seventh semiconductor layer has a smaller amount of impurities than the sixth semiconductor layer.

摘要翻译： 晶体管包含第一导电类型的第一半导体层和具有柱结构的漂移层，其中第一导电类型的第二半导体层和第二导电类型的第三半导体层在平行于 第一半导体层的表面。 第一导电类型的第四半导体层和第二导电类型的第五半导体层交替地设置并平行于漂移层。 第五半导体层的杂质量比第四半导体层大。 第一导电类型的第六半导体层和第二导电类型的第七半导体层交替地设置并平行于第四和第五半导体层。 第七半导体层的杂质量比第六半导体层少。