公开(公告)号：US06790733B1

公开(公告)日：2004-09-14

申请号：US10249296

申请日：2003-03-28

申请人： Wesley C. Natzle ,  Bruce B. Doris ,  Sadanand V. Deshpande ,  Renee T. Mo ,  Patricia A. O'Neil

发明人： Wesley C. Natzle ,  Bruce B. Doris ,  Sadanand V. Deshpande ,  Renee T. Mo ,  Patricia A. O'Neil

IPC分类号： H01L21336

CPC分类号： H01L29/6659 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/6653 ,  Y10S438/976

摘要： The present invention provides a method for preserving an oxide hard mask for the purpose of avoiding growth of epi Si on the gate stack during raised source/drain formation. The oxide hard mask is preserved in the present invention by utilizing a method which includes a chemical oxide removal processing step instead of an aqueous HF etchant.

摘要翻译： 本发明提供了一种保护氧化物硬掩模的方法，其目的是避免在升高的源极/漏极形成期间栅极叠层上的外延Si的生长。 通过利用包括化学氧化物去除处理步骤而不是水性HF蚀刻剂的方法在本发明中保存氧化物硬掩模。

公开(公告)号：US20080156257A1

公开(公告)日：2008-07-03

申请号：US11873074

申请日：2007-10-16

申请人： Sadanand V. Deshpande ,  Ying Li ,  Kevin E. Mello ,  Renee T. Mo ,  Wesley C. Natzle ,  Kirk D. Peterson ,  Robert J. Purtell

发明人： Sadanand V. Deshpande ,  Ying Li ,  Kevin E. Mello ,  Renee T. Mo ,  Wesley C. Natzle ,  Kirk D. Peterson ,  Robert J. Purtell

IPC分类号： B05C11/00

CPC分类号： H01L21/28518 ,  C23C16/0227 ,  H01L21/02057 ,  H01L21/28512 ,  H01L21/67207 ,  H01L21/67745

摘要： A cluster tool is provided for the implementing of a clustered and integrated surface pre-cleaning of the surface of semiconductor devices. More particularly, there is provided a cluster tool and a method of utilization thereof in an integrated semiconductor device surface pre-cleaning, which is directed towards a manufacturing aspect in which a chamber for performing a dry processing chemical oxide removal (COR) on the semiconductor device surface is clustered with other tools, such as a metal deposition tool for silicide or contact formation, including the provision of a vacuum transfer module in the cluster tool.

摘要翻译： 提供了一种集群工具，用于实现半导体器件表面的集群和集成表面预清洁。 更具体地，提供了一种集成工具及其在集成半导体器件表面预清洁中的应用方法，其针对制造方面，其中用于在半导体上执行干法处理化学氧化物去除（COR）的室 器件表面与诸如用于硅化物或接触形成的金属沉积工具的其它工具聚集，包括在簇工具中提供真空转移模块。

公开(公告)号：US07344983B2

公开(公告)日：2008-03-18

申请号：US10907061

申请日：2005-03-18

申请人： Sadanand V. Deshpande ,  Ying Li ,  Kevin E. Mello ,  Renee T. Mo ,  Wesley C. Natzle ,  Kirk D. Peterson ,  Robert J. Purtell

发明人： Sadanand V. Deshpande ,  Ying Li ,  Kevin E. Mello ,  Renee T. Mo ,  Wesley C. Natzle ,  Kirk D. Peterson ,  Robert J. Purtell

IPC分类号： H01L21/44

CPC分类号： H01L21/28518 ,  C23C16/0227 ,  H01L21/02057 ,  H01L21/28512 ,  H01L21/67207 ,  H01L21/67745

摘要： A cluster tool is provided for the implementing of a clustered and integrated surface pre-cleaning of the surface of semiconductor devices. More particularly, there is provided a cluster tool and a method of utilization thereof in an integrated semiconductor device surface pre-cleaning, which is directed towards a manufacturing aspect in which a chamber for performing a dry processing chemical oxide removal (COR) on the semiconductor device surface is clustered with other tools, such as a metal deposition tool for silicide or contact formation, including the provision of a vacuum transfer module in the cluster tool.

摘要翻译： 提供了一种集群工具，用于实现半导体器件表面的集群和集成表面预清洁。 更具体地，提供了一种集成工具及其在集成半导体器件表面预清洁中的应用方法，其针对制造方面，其中用于在半导体上执行干法处理化学氧化物去除（COR）的室 器件表面与诸如用于硅化物或接触形成的金属沉积工具的其它工具聚集，包括在簇工具中提供真空转移模块。

公开(公告)号：US20080188089A1

公开(公告)日：2008-08-07

申请号：US11671668

申请日：2007-02-06

申请人： Anthony I. Chou ,  Sadanand V. Deshpande ,  Renee T. Mo ,  Shreesh Narasimha ,  Katsunori Onishi ,  Dominic Schepis

发明人： Anthony I. Chou ,  Sadanand V. Deshpande ,  Renee T. Mo ,  Shreesh Narasimha ,  Katsunori Onishi ,  Dominic Schepis

IPC分类号： H01L21/31

CPC分类号： H01L21/32105 ,  H01L21/28035 ,  H01L21/28247

摘要： A method for reducing top notching effects in pre-doped gate structures includes subjecting an etched, pre-doped gate stack structure to a re-oxidation process, the re-oxidation process comprising a radical assisted re-oxidation process so as to result in the formation of an oxide layer over vertical sidewall and horizontal top surfaces of the etched gate stack structure. The resulting oxide layer has a substantially uniform thickness independent of grain boundary orientations of the gate stack structure and independent of the concentration and location of dopant material present therein.

摘要翻译： 用于减少预掺杂栅极结构中的顶部切口效应的方法包括将经蚀刻的预掺杂栅极堆叠结构进行再氧化处理，所述再氧化工艺包括自由基辅助再氧化工艺，以便导致 在蚀刻的栅堆叠结构的垂直侧壁和水平顶表面上形成氧化物层。 所得到的氧化物层具有与栅极堆叠结构的晶界取向无关的基本均匀的厚度，而与其中存在的掺杂剂材料的浓度和位置无关。

公开(公告)号：US09252018B2

公开(公告)日：2016-02-02

申请号：US13571977

申请日：2012-08-10

申请人： Renee T. Mo ,  Wesley C. Natzle ,  Vijay Narayanan ,  Jeffrey W. Sleight

发明人： Renee T. Mo ,  Wesley C. Natzle ,  Vijay Narayanan ,  Jeffrey W. Sleight

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

CPC分类号： H01L21/28088 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/7833

摘要： A transistor is provided that includes a silicon layer with a source region and a drain region, a gate stack disposed on the silicon layer between the source region and the drain region, an L shaped gate encapsulation layer disposed on sidewalls of the gate stack, and a spacer disposed above the horizontal portion of the gate encapsulation layer and adjacent to the vertical portion of the gate encapsulation layer. The gate stack has a first layer of high dielectric constant material, a second layer comprising a metal or metal alloy, and a third layer comprising silicon or polysilicon. The gate encapsulation layer has a vertical portion covering the sidewalls of the first, second, and third layers of the gate stack and a horizontal portion covering a portion of the silicon layer that is adjacent to the gate stack.

摘要翻译： 提供晶体管，其包括具有源极区和漏极区的硅层，设置在源极区和漏极区之间的硅层上的栅极堆叠，设置在栅极堆叠的侧壁上的L形栅极封装层，以及 设置在栅极封装层的水平部分上方并且与栅极封装层的垂直部分相邻的间隔物。 栅堆叠具有第一层高介电常数材料，第二层包括金属或金属合金，以及第三层包括硅或多晶硅。 栅极封装层具有覆盖栅极堆叠的第一，第二和第三层的侧壁的垂直部分和覆盖与栅极叠层相邻的硅层的一部分的水平部分。

公开(公告)号：US07955926B2

公开(公告)日：2011-06-07

申请号：US12055682

申请日：2008-03-26

申请人： Wesley C. Natzle ,  Renee T. Mo ,  Rashmi Jha ,  Kathryn T. Schonenberg ,  Richard A. Conti

发明人： Wesley C. Natzle ,  Renee T. Mo ,  Rashmi Jha ,  Kathryn T. Schonenberg ,  Richard A. Conti

IPC分类号： H01L21/00

CPC分类号： H01L21/76224 ,  H01L21/28123 ,  H01L29/517

摘要： In one embodiment, the present invention provides a method of fabricating a semiconducting device that includes providing a substrate including at least one semiconducting region and at least one oxygen source region; forming an oxygen barrier material atop portions of an upper surface of the at least one oxygen region; forming a high-k gate dielectric on the substrate including the at least one semiconducting region, wherein oxygen barrier material separates the high-k gate dielectric from the at least one oxygen source material; and forming a gate conductor atop the high-k gate dielectric.

摘要翻译： 在一个实施例中，本发明提供一种制造半导体器件的方法，其包括提供包括至少一个半导体区域和至少一个氧源区域的衬底; 在所述至少一个氧区的上表面的部分顶部形成氧阻隔材料; 在包括所述至少一个半导体区域的衬底上形成高k栅极电介质，其中氧阻挡材料将所述高k栅极电介质与所述至少一个氧源材料分离; 并在高k栅极电介质的顶部形成栅极导体。

公开(公告)号：US20100244206A1

公开(公告)日：2010-09-30

申请号：US12414794

申请日：2009-03-31

申请人： Huiming Bu ,  Michael P. Chudzik ,  Wei He ,  Rashmi Jha ,  Young-Hee Kim ,  Siddarth A. Krishnan ,  Renee T. Mo ,  Naim Moumen ,  Wesley C. Natzle

发明人： Huiming Bu ,  Michael P. Chudzik ,  Wei He ,  Rashmi Jha ,  Young-Hee Kim ,  Siddarth A. Krishnan ,  Renee T. Mo ,  Naim Moumen ,  Wesley C. Natzle

IPC分类号： H01L23/00 ,  H01L21/314

CPC分类号： H01L21/28202 ,  H01L21/28176 ,  H01L21/28185 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a device includes providing a substrate, forming an interfacial layer on the substrate, depositing a high-k dielectric layer on the interfacial layer, depositing an oxygen scavenging layer on the high-k dielectric layer and performing an anneal. A high-k metal gate transistor includes a substrate, an interfacial layer on the substrate, a high-k dielectric layer on the interfacial layer and an oxygen scavenging layer on the high-k dielectric layer.

摘要翻译： 形成器件的方法包括提供衬底，在衬底上形成界面层，在界面层上沉积高k电介质层，在高k电介质层上沉积氧气清除层并执行退火。 高k金属栅极晶体管包括衬底，衬底上的界面层，界面层上的高k电介质层和高k电介质层上的氧清除层。

公开(公告)号：US07498271B1

公开(公告)日：2009-03-03

申请号：US12145035

申请日：2008-06-24

申请人： Ricardo A. Donaton ,  Rashmi Jha ,  Siddarth A. Krishnan ,  Xi Li ,  Renee T. Mo ,  Naim Moumen ,  Wesley C. Natzle ,  Ravikumar Ramachandran ,  Richard S. Wise

发明人： Ricardo A. Donaton ,  Rashmi Jha ,  Siddarth A. Krishnan ,  Xi Li ,  Renee T. Mo ,  Naim Moumen ,  Wesley C. Natzle ,  Ravikumar Ramachandran ,  Richard S. Wise

IPC分类号： H01L21/31

CPC分类号： H01L21/31138 ,  H01L21/28202 ,  H01L21/31155 ,  H01L21/823828 ,  H01L21/823878 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： The present invention, in one embodiment, provides a method of forming a gate structure including providing a substrate including a semiconducting device region, a high-k dielectric material present atop the semiconducting device region, and a metal gate conductor atop the high-k dielectric material, applying a photoresist layer atop the metal gate conductor; patterning the photoresist layer to provide an etch mask overlying a portion of the metal gate conductor corresponding to a gate stack; etching the metal gate conductor and the high-k dielectric material selective to the etch mask; and removing the etch mask with a substantially oxygen free nitrogen based plasma.

摘要翻译： 本发明在一个实施例中提供了一种形成栅极结构的方法，该栅极结构包括提供包括半导体器件区域的衬底，在半导体器件区域顶部存在的高k电介质材料以及高k电介质顶部的金属栅极导体 材料，在金属栅极导体顶上施加光致抗蚀剂层; 图案化光致抗蚀剂层以提供覆盖对应于栅极堆叠的金属栅极导体的一部分的蚀刻掩模; 蚀刻对蚀刻掩模有选择性的金属栅极导体和高k电介质材料; 并用基本上不含氧的氮气等离子体去除蚀刻掩模。

公开(公告)号：US09263276B2

公开(公告)日：2016-02-16

申请号：US12551292

申请日：2009-11-18

申请人： Renee T. Mo ,  Wesley C. Natzle ,  Vijay Narayanan ,  Jeffrey W. Sleight

发明人： Renee T. Mo ,  Wesley C. Natzle ,  Vijay Narayanan ,  Jeffrey W. Sleight

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

CPC分类号： H01L21/28088 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/7833

摘要： A transistor is provided that includes a silicon layer with a source region and a drain region, a gate stack disposed on the silicon layer between the source region and the drain region, an L shaped gate encapsulation layer disposed on sidewalls of the gate stack, and a spacer disposed above the horizontal portion of the gate encapsulation layer and adjacent to the vertical portion of the gate encapsulation layer. The gate stack has a first layer of high dielectric constant material, a second layer comprising a metal or metal alloy, and a third layer comprising silicon or polysilicon. The gate encapsulation layer has a vertical portion covering the sidewalls of the first, second, and third layers of the gate stack and a horizontal portion covering a portion of the silicon layer that is adjacent to the gate stack.

公开(公告)号：US20090243031A1

公开(公告)日：2009-10-01

申请号：US12055682

申请日：2008-03-26

申请人： Wesley C. Natzle ,  Renee T. Mo ,  Rashmi Jha ,  Kathryn T. Schonenberg ,  Richard A. Conti

发明人： Wesley C. Natzle ,  Renee T. Mo ,  Rashmi Jha ,  Kathryn T. Schonenberg ,  Richard A. Conti

IPC分类号： H01L29/49 ,  H01L21/441

CPC分类号： H01L21/76224 ,  H01L21/28123 ,  H01L29/517

摘要： In one embodiment, the present invention provides a method of fabricating a semiconducting device that includes providing a substrate including at least one semiconducting region and at least one oxygen source region; forming an oxygen barrier material atop portions of an upper surface of the at least one oxygen region; forming a high-k gate dielectric on the substrate including the at least one semiconducting region, wherein oxygen barrier material separates the high-k gate dielectric from the at least one oxygen source material; and forming a gate conductor atop the high-k gate dielectric.

摘要翻译： 在一个实施例中，本发明提供一种制造半导体器件的方法，其包括提供包括至少一个半导体区域和至少一个氧源区域的衬底; 在所述至少一个氧区的上表面的部分顶部形成氧阻隔材料; 在包括所述至少一个半导体区域的衬底上形成高k栅极电介质，其中氧阻挡材料将所述高k栅极电介质与所述至少一个氧源材料分离; 并在高k栅极电介质的顶部形成栅极导体。