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    High-k/metal gate transistor with L-shaped gate encapsulation layer
    6.
    发明授权
    High-k/metal gate transistor with L-shaped gate encapsulation layer 有权
    具有L形栅极封装层的高k /金属栅极晶体管

    公开(公告)号：US09252018B2

    公开(公告)日：2016-02-02

    申请号：US13571977

    申请日：2012-08-10

    申请人： Renee T. Mo ,  Wesley C. Natzle ,  Vijay Narayanan ,  Jeffrey W. Sleight

    发明人： Renee T. Mo ,  Wesley C. Natzle ,  Vijay Narayanan ,  Jeffrey W. Sleight

    IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

    CPC分类号： H01L21/28088 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/7833

    摘要： A transistor is provided that includes a silicon layer with a source region and a drain region, a gate stack disposed on the silicon layer between the source region and the drain region, an L shaped gate encapsulation layer disposed on sidewalls of the gate stack, and a spacer disposed above the horizontal portion of the gate encapsulation layer and adjacent to the vertical portion of the gate encapsulation layer. The gate stack has a first layer of high dielectric constant material, a second layer comprising a metal or metal alloy, and a third layer comprising silicon or polysilicon. The gate encapsulation layer has a vertical portion covering the sidewalls of the first, second, and third layers of the gate stack and a horizontal portion covering a portion of the silicon layer that is adjacent to the gate stack.

    摘要翻译： 提供晶体管，其包括具有源极区和漏极区的硅层，设置在源极区和漏极区之间的硅层上的栅极堆叠，设置在栅极堆叠的侧壁上的L形栅极封装层，以及 设置在栅极封装层的水平部分上方并且与栅极封装层的垂直部分相邻的间隔物。 栅堆叠具有第一层高介电常数材料，第二层包括金属或金属合金，以及第三层包括硅或多晶硅。 栅极封装层具有覆盖栅极堆叠的第一，第二和第三层的侧壁的垂直部分和覆盖与栅极叠层相邻的硅层的一部分的水平部分。

    Structure and method to control oxidation in high-k gate structures
    7.
    发明授权
    Structure and method to control oxidation in high-k gate structures 有权
    控制高k栅极结构氧化的结构和方法

    公开(公告)号：US07955926B2

    公开(公告)日：2011-06-07

    申请号：US12055682

    申请日：2008-03-26

    申请人： Wesley C. Natzle ,  Renee T. Mo ,  Rashmi Jha ,  Kathryn T. Schonenberg ,  Richard A. Conti

    发明人： Wesley C. Natzle ,  Renee T. Mo ,  Rashmi Jha ,  Kathryn T. Schonenberg ,  Richard A. Conti

    IPC分类号： H01L21/00

    CPC分类号： H01L21/76224 ,  H01L21/28123 ,  H01L29/517

    摘要： In one embodiment, the present invention provides a method of fabricating a semiconducting device that includes providing a substrate including at least one semiconducting region and at least one oxygen source region; forming an oxygen barrier material atop portions of an upper surface of the at least one oxygen region; forming a high-k gate dielectric on the substrate including the at least one semiconducting region, wherein oxygen barrier material separates the high-k gate dielectric from the at least one oxygen source material; and forming a gate conductor atop the high-k gate dielectric.

    摘要翻译： 在一个实施例中，本发明提供一种制造半导体器件的方法，其包括提供包括至少一个半导体区域和至少一个氧源区域的衬底; 在所述至少一个氧区的上表面的部分顶部形成氧阻隔材料; 在包括所述至少一个半导体区域的衬底上形成高k栅极电介质，其中氧阻挡材料将所述高k栅极电介质与所述至少一个氧源材料分离; 并在高k栅极电介质的顶部形成栅极导体。

    HIGH-K/METAL GATE TRANSISTOR WITH L-SHAPED GATE ENCAPSULATION LAYER
    8.
    发明申请
    HIGH-K/METAL GATE TRANSISTOR WITH L-SHAPED GATE ENCAPSULATION LAYER 有权
    具有L形门盖的高K /金属栅极晶体管

    公开(公告)号：US20110115032A1

    公开(公告)日：2011-05-19

    申请号：US12551292

    申请日：2009-11-18

    申请人： RENEE T. MO ,  Wesley C. Natzle ,  Vijay Narayanan ,  Jeffrey W. Sleight

    发明人： RENEE T. MO ,  Wesley C. Natzle ,  Vijay Narayanan ,  Jeffrey W. Sleight

    IPC分类号： H01L29/78 ,  H01L21/28

    CPC分类号： H01L21/28088 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/7833

    摘要： A transistor is provided that includes a silicon layer with a source region and a drain region, a gate stack disposed on the silicon layer between the source region and the drain region, an L shaped gate encapsulation layer disposed on sidewalls of the gate stack, and a spacer disposed above the horizontal portion of the gate encapsulation layer and adjacent to the vertical portion of the gate encapsulation layer. The gate stack has a first layer of high dielectric constant material, a second layer comprising a metal or metal alloy, and a third layer comprising silicon or polysilicon. The gate encapsulation layer has a vertical portion covering the sidewalls of the first, second, and third layers of the gate stack and a horizontal portion covering a portion of the silicon layer that is adjacent to the gate stack.

    摘要翻译： 提供晶体管，其包括具有源极区和漏极区的硅层，设置在源极区和漏极区之间的硅层上的栅极堆叠，设置在栅极堆叠的侧壁上的L形栅极封装层，以及 设置在栅极封装层的水平部分上方并且与栅极封装层的垂直部分相邻的间隔物。 栅堆叠具有第一层高介电常数材料，第二层包括金属或金属合金，以及第三层包括硅或多晶硅。 栅极封装层具有覆盖栅极堆叠的第一，第二和第三层的侧壁的垂直部分和覆盖与栅极叠层相邻的硅层的一部分的水平部分。