公开(公告)号：US5184272A

公开(公告)日：1993-02-02

申请号：US500881

申请日：1990-03-29

申请人： Koichi Suda ,  Hitoshi Matsuzaki ,  Masayuki Wada ,  Shoichi Ozeki

发明人： Koichi Suda ,  Hitoshi Matsuzaki ,  Masayuki Wada ,  Shoichi Ozeki

IPC分类号： H01L27/02 ,  H03K17/06 ,  H03K17/082

CPC分类号： H03K17/063 ,  H01L27/0251 ,  H03K17/0822

摘要： A switching circuit providing detection circuit for detecting a current which flows through a main P-channel MOSFET detection of a floating voltage dependent upon a power supply potential, a reference-voltage generating circuit for generating a reference voltage which is a floating voltage dependent upon the power supply potential and has a constant value independently of variations in power supply potential, a comparator circuit operated on a supply voltage which is a floating voltage dependent upon the power supply potential, for comparing a detected voltage from the detection circuit with the reference voltage from the reference-voltage generating means, to convert the detected voltage into a logic voltage signal (i.e., a bi-level voltage signal and a conversion circuit for converting the logic voltage outputted by the comparator circuit into a voltage measured from a ground potential.

摘要翻译： 提供检测电路的开关电路，用于检测根据电源电位检测流过主P沟道MOSFET检测浮置电压的电流;基准电压产生电路，用于产生基于电压的浮置电压的参考电压 电源电位，并且具有独立于电源电位变化的恒定值，比较器电路在作为取决于电源电位的浮动电压的电源电压下工作，用于将来自检测电路的检测电压与来自 参考电压产生装置将检测到的电压转换为逻辑电压信号（即，双电平电压信号和用于将由比较器电路输出的逻辑电压转换为从地电位测量的电压的转换电路）。

公开(公告)号：US06580108B1

公开(公告)日：2003-06-17

申请号：US09497213

申请日：2000-02-03

申请人： Tomoyuki Utsumi ,  Shoichi Ozeki ,  Koichi Suda

发明人： Tomoyuki Utsumi ,  Shoichi Ozeki ,  Koichi Suda

IPC分类号： H01L2976

CPC分类号： H01L29/4232 ,  H01L29/42312 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/7393 ,  H01L29/7395 ,  H01L29/7801 ,  H01L29/7809 ,  H01L29/7816

摘要： An insulated gate transistor comprising a first semiconductor region, a second semiconductor region includes plural portions, a third semiconductor region, a fourth semiconductor region, a first insulation layer, control electrodes, a first main electrode, and a second main electrode, wherein a metallic wiring layer is provided on the first main surface plane via an insulating layer, plural regions insulated from the first main electrode are provided through said first main electrode, and the metallic wiring layer is connected electrically to the control electrode through the insulating layer via the region insulated from the main electrode.

摘要翻译： 一种绝缘栅晶体管，包括第一半导体区域，第二半导体区域包括多个部分，第三半导体区域，第四半导体区域，第一绝缘层，控制电极，第一主电极和第二主电极，其中金属 布线层经由绝缘层设置在第一主表面上，通过所述第一主电极设置与第一主电极绝缘的多个区域，并且金属布线层经由该区域通过绝缘层与控制电极电连接 与主电极绝缘。

公开(公告)号：US6040827A

公开(公告)日：2000-03-21

申请号：US890994

申请日：1997-07-10

申请人： Kazuhiro Shiina ,  Koji Kawamoto ,  Masato Miura ,  Hitoshi Ohura ,  Shoichi Ozeki ,  Noboru Akiyama ,  Kunihoro Nunomura ,  Minehiro Nemoto ,  Masahiro Iwamura

发明人： Kazuhiro Shiina ,  Koji Kawamoto ,  Masato Miura ,  Hitoshi Ohura ,  Shoichi Ozeki ,  Noboru Akiyama ,  Kunihoro Nunomura ,  Minehiro Nemoto ,  Masahiro Iwamura

IPC分类号： G09G3/20 ,  G09G3/28 ,  G09G3/288 ,  G09G3/30 ,  H02P6/08 ,  G09G5/00

CPC分类号： H02P6/085 ,  G09G3/20 ,  G09G3/296 ,  G09G2310/0267 ,  G09G2310/0275 ,  G09G2310/0289 ,  G09G3/30

摘要： A driver circuit wherein a first switching element and a second switching element are totem-pole-connected, wherein the totem pole connection is connected at its one end, node and other end with a power source, an output to a load and a reference potential, respectively, wherein the first switching element is connected between the one end and the node, wherein the second switching element is connected between the node and the other end, and wherein a third switching element is connected between the one end of the totem pole connection and the control terminal of the first switching element.

摘要翻译： 一种驱动器电路，其中第一开关元件和第二开关元件是图腾极连接的，其中图腾柱连接在其一端，节点和另一端与电源连接，输出到负载和参考电位 ，其中所述第一开关元件连接在所述一端和所述节点之间，其中所述第二开关元件连接在所述节点和所述另一端之间，并且其中第三开关元件连接在所述图腾柱连接的所述一端 和第一开关元件的控制端子。

公开(公告)号：US4665505A

公开(公告)日：1987-05-12

申请号：US685552

申请日：1984-12-24

申请人： Nobuaki Miyakawa ,  Yoshiaki Yazawa ,  Shoichi Ozeki ,  Kinya Mitsumoto

发明人： Nobuaki Miyakawa ,  Yoshiaki Yazawa ,  Shoichi Ozeki ,  Kinya Mitsumoto

IPC分类号： G11C11/413 ,  G11C7/10 ,  G11C11/40

CPC分类号： G11C7/1096 ,  G11C7/1078

摘要： A write circuit for a semiconductor storage device which comprises a data output stage constructed by a composite circuit including at least one MOS transistor logic circuit and bipolar transistor. The Mos transistor circuit operates in response to an input signal to control the on-off states of at least one of the bipolar transistors. The write circuit implements less power consumption.

摘要翻译： 一种用于半导体存储装置的写入电路，包括由包括至少一个MOS晶体管逻辑电路和双极晶体管的复合电路构成的数据输出级。 Mos晶体管电路响应于输入信号而工作，以控制至少一个双极晶体管的导通截止状态。 写入电路实现更少的功耗。

公开(公告)号：US5818281A

公开(公告)日：1998-10-06

申请号：US528887

申请日：1995-09-15

申请人： Hitoshi Ohura ,  Koji Kawamoto ,  Shoichi Ozeki

发明人： Hitoshi Ohura ,  Koji Kawamoto ,  Shoichi Ozeki

IPC分类号： H02M7/537 ,  H02M1/08 ,  H03K17/00 ,  H03K17/082 ,  H03K17/16 ,  H03K17/56

CPC分类号： H02M7/538 ,  H03K17/0828 ,  H03K2217/0036

摘要： For a semiconductor circuit having one or more semiconductor devices, such as an IGBT, a turn-ON prevention circuit is provided for each device which prevents the device from turning ON during OFF times thereof, due to the presence of a transient voltage (dV/dt) across the main terminals of the device. In accordance with such a scheme, a MOSFET is connected between the insulated-gate electrode and emitter of the IGBT, and a capacitor, for example, is connected between the gate of the MOSFET and a sufficient electric potential to thereby effect a temporary turn-ON of the MOSFET to remove parasitic charge build-up in the IGBT before such charge build-up has reached a potential of the turn-ON threshold of the IGBT during OFF times of the IGBT. The capacitance element can be constituted by a MOSFET, namely, the capacitance across the gate-to-drain of an additional MOSFET. As a result, therefore, power consumption can be kept sufficiently small and the chip area required for implementing the circuit, such as, in a monolithic construction can be reduced. Further, the turn-ON prevention scheme can be applied to MOSFET devices rather than IGBTs.

摘要翻译： 对于具有一个或多个半导体器件（例如IGBT）的半导体电路，由于存在瞬态电压（dV / V），每个器件提供导通保护电路，以防止器件在其OFF时间期间导通， dt）跨越器件的主端子。 根据这种方案，MOSFET连接在IGBT的绝缘栅电极和发射极之间，并且电容器例如连接在MOSFET的栅极和足够的电势之间，从而实现暂时的转换， 在IGBT的截止时间之前，这种电荷积聚已经达到IGBT的导通阈值的电位，从而去除MOSFET中的寄生电荷积聚。 电容元件可以由MOSFET构成，即额外MOSFET的栅极到漏极之间的电容。 因此，因此能够将功耗保持在足够小，并且可以减少实现电路所需的芯片面积，例如在单片结构中。 此外，导通保护方案可以应用于MOSFET器件而不是IGBT。