公开(公告)号：US06528378B2

公开(公告)日：2003-03-04

申请号：US10134522

申请日：2002-04-30

申请人： Koji Hirata ,  Hiroyuki Takazawa

发明人： Koji Hirata ,  Hiroyuki Takazawa

IPC分类号： H01L21331

CPC分类号： H01L29/66318 ,  H01L29/7371 ,  H03F3/195 ,  H03F3/60

摘要： To provide a super high-speed heterojunction bipolar transistor, a semiconductor device including such a heterojunction bipolar transistor has a structure wherein a subcollector layer, collector layer, base layer, emitter layer (InGaP layer) and emitter cap layer are successively formed in predetermined shapes a surface of a semi-insulating GaAs substrate, an inner edge part of a base electrode overlaps a periphery of the emitter layer, and the base electrode is electrically connected to the base layer by an alloy layer formed by alloying the emitter layer under the base electrode. The emitter layer is selectively formed on the base layer. The base electrode extends from the peripheral part of the emitter layer across the base layer, and the alloy layer extends to a midway depth of the base layer. The edge of the base layer is situated further inside than the outer edge of the base electrode.

公开(公告)号：US06392258B1

公开(公告)日：2002-05-21

申请号：US09516160

申请日：2000-02-29

申请人： Koji Hirata ,  Hiroyuki Takazawa

发明人： Koji Hirata ,  Hiroyuki Takazawa

IPC分类号： H01L29737

CPC分类号： H01L29/66318 ,  H01L29/7371 ,  H03F3/195 ,  H03F3/60

摘要： To provide a super high-speed heterojunction bipolar transistor, a semiconductor device including such a heterojunction bipolar transistor has a structure wherein a subcollector layer, collector layer, base layer, emitter layer (InGaP layer) and emitter cap layer are successively formed in predetermined shapes a surface of a semi-insulating GaAs substrate, an inner edge part of a base electrode overlaps a periphery of the emitter layer, and the base electrode is electrically connected to the base layer by an alloy layer formed by alloying the emitter layer under the base electrode. The emitter layer is selectively formed on the base layer. The base electrode extends from the peripheral part of the emitter layer across the base layer, and the alloy layer extends to a midway depth of the base layer. The edge of the base layer is situated further inside than the outer edge of the base electrode.

摘要翻译： 为了提供超高速异质结双极晶体管，包括这种异质结双极晶体管的半导体器件具有其中以预定形状连续形成子集电极层，集电极层，基极层，发射极层（InGaP层）和发射极盖层的结构 半绝缘GaAs衬底的表面，基极的内边缘部分与发射极层的周边重叠，并且基极通过合金层与基底层电连接，所述合金层通过将发射极层合在基底 电极。 发射极层选择性地形成在基底层上。 基极从发射极层的周边部分穿过基底层延伸，合金层延伸到基底层的中间深度。 基层的边缘比基极的外边缘更靠内侧。

公开(公告)号：US08385847B2

公开(公告)日：2013-02-26

申请号：US12929940

申请日：2011-02-25

申请人： Takashi Ogawa ,  Shinichiro Takatani ,  Shigeki Koya ,  Hiroyuki Takazawa ,  Shinya Osakabe ,  Akishige Nakajima ,  Yasushi Shigeno

发明人： Takashi Ogawa ,  Shinichiro Takatani ,  Shigeki Koya ,  Hiroyuki Takazawa ,  Shinya Osakabe ,  Akishige Nakajima ,  Yasushi Shigeno

IPC分类号： H04B1/44

CPC分类号： H01L27/0605 ,  H01L27/0629 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/7783 ,  H01L2924/0002 ,  H01L2924/00

摘要： A switching element is provided that realizes an stabilize a potential between the gates of the multi-gates without an increase in the insertion loss, and an antenna switch circuit and a radio frequency module each using the switch element. The switching element includes two ohmic electrodes 39, 40 formed on a semiconductor substrate, at least two gate electrodes 41, 42 disposed between the two ohmic electrodes, and a conductive region 45 disposed between the adjacent gate electrodes among the at least two gate electrodes, a field effective transistor being structured by the two ohmic electrodes, the at least two gate electrodes, and the conductive region. The conductive region has a wider portion that is wider in width than the conductive region interposed between the adjacent gate electrodes on one end thereof. The distance between the adjacent gate electrodes is narrower than the width of the wider portion. Resistors 44, 46 are connected in series between the two ohmic electrodes through the wider portion.

公开(公告)号：US07768066B2

公开(公告)日：2010-08-03

申请号：US12179549

申请日：2008-07-24

申请人： Hidekatsu Onose ,  Hiroyuki Takazawa

发明人： Hidekatsu Onose ,  Hiroyuki Takazawa

IPC分类号： H01L29/94

CPC分类号： H01L29/7828 ,  H01L25/18 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7391 ,  H01L2924/0002 ,  H01L2924/00

摘要： A UMOSFET is capable of reducing a threshold voltage and producing a large saturation current. A typical UMOSFET according to the present invention includes: an N+ type SiC substrate constituting a drain layer; an N− type SiC layer that is in contact with the drain layer and constitutes a drift layer; a P type body layer formed on the drift layer and being a semiconductor layer; an N+ type SiC layer constituting a source layer; a trench extending from the source layer to a predetermined location placed in the drift layer; a P type electric field relaxation region provided around and outside a bottom portion of the trench; and a channel region extending from the N+ type source layer to the P type electric field relaxation region and having an impurity concentration higher than that of the N− type drift layer and lower than that of the P type body layer.

摘要翻译： UMOSFET能够降低阈值电压并产生大的饱和电流。 根据本发明的典型的UMOSFET包括：构成漏极层的N +型SiC衬底; 与漏极层接触并构成漂移层的N型SiC层; 形成在所述漂移层上并且是半导体层的P型体层; 构成源极层的N +型SiC层; 从源极层延伸到放置在漂移层中的预定位置的沟槽; 设置在沟槽的底部周围和外侧的P型电场弛豫区域; 以及从N +型源极层向P型电场弛豫区域延伸并且杂质浓度高于N型漂移层的杂质浓度并低于P型体层的沟道区域。

公开(公告)号：US20090104881A1

公开(公告)日：2009-04-23

申请号：US12314644

申请日：2008-12-15

申请人： Takashi Ogawa ,  Shinichiro Takatani ,  Shigeki Koya ,  Hiroyuki Takazawa ,  Shinya Osakabe ,  Akishige Nakajima ,  Yasushi Shigeno

发明人： Takashi Ogawa ,  Shinichiro Takatani ,  Shigeki Koya ,  Hiroyuki Takazawa ,  Shinya Osakabe ,  Akishige Nakajima ,  Yasushi Shigeno

IPC分类号： H04B1/44 ,  H01L29/778

CPC分类号： H01L27/0605 ,  H01L27/0629 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/7783 ,  H01L2924/0002 ,  H01L2924/00

摘要： A switching element is provided that realizes an stabilize a potential between the gates of the multi-gates without an increase in the insertion loss, and an antenna switch circuit and a radio frequency module each using the switch element. The switching element includes two ohmic electrodes 39, 40 formed on a semiconductor substrate, at least two gate electrodes 41, 42 disposed between the two ohmic electrodes, and a conductive region 45 disposed between the adjacent gate electrodes among the at least two gate electrodes, a field effective transistor being structured by the two ohmic electrodes, the at least two gate electrodes, and the conductive region. The conductive region has a wider portion that is wider in width than the conductive region interposed between the adjacent gate electrodes on one end thereof. The distance between the adjacent gate electrodes is narrower than the width of the wider portion. Resistors 44, 46 are connected in series between the two ohmic electrodes through the wider portion.

摘要翻译： 提供了一种开关元件，其实现了在不增加插入损耗的情况下使多栅极的栅极之间的电位稳定，并且每个使用开关元件的天线开关电路和射频模块。 开关元件包括形成在半导体衬底上的两个欧姆电极39,40，设置在两个欧姆电极之间的至少两个栅极电极41,42以及设置在至少两个栅电极之间的相邻栅电极之间的导电区域45， 场效应晶体管由两个欧姆电极，至少两个栅极电极和导电区域构成。 导电区域的宽度部分的宽度比插入在其一端的相邻栅电极之间的导电区域宽。 相邻栅电极之间的距离比较宽部分的宽度窄。 电阻器44,46通过较宽部分串联连接在两个欧姆电极之间。

公开(公告)号：US07307298B2

公开(公告)日：2007-12-11

申请号：US10989388

申请日：2004-11-17

申请人： Masao Yamane ,  Atsushi Kurokawa ,  Shinya Osakabe ,  Eigo Tange ,  Yasushi Shigeno ,  Hiroyuki Takazawa

发明人： Masao Yamane ,  Atsushi Kurokawa ,  Shinya Osakabe ,  Eigo Tange ,  Yasushi Shigeno ,  Hiroyuki Takazawa

IPC分类号： H01L29/80 ,  H01L31/12

CPC分类号： H01L29/7787 ,  H01L21/8252 ,  H01L27/0605

摘要： The present invention miniaturizes a HEMT element used as a switching element in a radio frequency module. A single gate electrode 17 is formed in an active region defined by an element separation portion 9 on a main surface of a substrate 1 comprising GaAs. The gate electrode 17 is patterned so as to extend in the vertical direction of the page surface between source electrodes 13 and drain electrodes 14, and to extend in left and right directions at other portions. Thus, the ratio of the gate electrode 17 disposed outside the active region is reduced, and the area of a gate pad 17A is reduced.

摘要翻译： 本发明将用作射频模块中的开关元件的HEMT元件小型化。 单个栅极电极17形成在由包含GaAs的基板1的主表面上的元件分离部分9限定的有源区域中。 栅电极17被图案化以在源电极13和漏电极14之间的页表面的垂直方向上延伸，并且在其它部分沿左右方向延伸。 因此，设置在有源区域之外的栅电极17的比率减小，并且栅极焊盘17A的面积减小。

公开(公告)号：US20060118951A1

公开(公告)日：2006-06-08

申请号：US11291815

申请日：2005-12-02

申请人： Takashi Ogawa ,  Shinichiro Takatani ,  Shigeki Koya ,  Hiroyuki Takazawa ,  Shinya Osakabe ,  Akishige Nakajima ,  Yasushi Shigeno

发明人： Takashi Ogawa ,  Shinichiro Takatani ,  Shigeki Koya ,  Hiroyuki Takazawa ,  Shinya Osakabe ,  Akishige Nakajima ,  Yasushi Shigeno

IPC分类号： H01L23/34

CPC分类号： H01L27/0605 ,  H01L27/0629 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/7783 ,  H01L2924/0002 ,  H01L2924/00

摘要： A switching element is provided that realizes an stabilize a potential between the gates of the multi-gates without an increase in the insertion loss, and an antenna switch circuit and a radio frequency module each using the switch element. The switching element includes two ohmic electrodes 39, 40 formed on a semiconductor substrate, at least two gate electrodes 41, 42 disposed between the two ohmic electrodes, and a conductive region 45 disposed between the adjacent gate electrodes among the at least two gate electrodes, a field effective transistor being structured by the two ohmic electrodes, the at least two gate electrodes, and the conductive region. The conductive region has a wider portion that is wider in width than the conductive region interposed between the adjacent gate electrodes on one end thereof. The distance between the adjacent gate electrodes is narrower than the width of the wider portion. Resistors 44, 46 are connected in series between the two ohmic electrodes through the wider portion.

公开(公告)号：US06724020B2

公开(公告)日：2004-04-20

申请号：US10420764

申请日：2003-04-23

申请人： Hiroyuki Takazawa ,  Tohru Oka ,  Isao Ohbu ,  Yoshinori Imamura

发明人： Hiroyuki Takazawa ,  Tohru Oka ,  Isao Ohbu ,  Yoshinori Imamura

IPC分类号： H01L31109

CPC分类号： H01L29/7371 ,  H03F3/60

摘要： A semiconductor device comprising a bipolar transistor having an emitter layer consisting of a semiconductor containing indium, and a protective insulating film containing silicon and oxygen which is formed on the surface of the guard ring of the emitter layer, wherein the protective insulating film has a density of oxygen of less than 7×1022 cm−3. This semiconductor device prevents performance deterioration and ensures high performance in a power amplifier.

摘要翻译： 一种半导体器件，包括具有由包含铟的半导体构成的发射极层的双极晶体管和形成在发射极层的保护环的表面上的含有氧和氧的保护绝缘膜，其中该保护绝缘膜具有密度 的氧气小于7×10 22 cm -3。 该半导体器件防止性能恶化并确保功率放大器的高性能。

公开(公告)号：US5739559A

公开(公告)日：1998-04-14

申请号：US798450

申请日：1997-02-10

申请人： Osamu Kagaya ,  Hiroyuki Takazawa

发明人： Osamu Kagaya ,  Hiroyuki Takazawa

IPC分类号： H01L21/76 ,  H01L27/06 ,  H01L27/095 ,  H01L29/10 ,  H01L31/0328 ,  H01L29/167 ,  H01L31/0336

CPC分类号： H01L27/0605 ,  H01L29/1075

摘要： A compound semiconductor integrated circuit having a high resistance layer consisting of a compound semiconductor to which oxygen is added as an impurity and an undoped compound semiconductor layer which are formed between a semi-insulating substrate and field effect transistors formed thereon sequentially from the semi-insulating substrate side is suited to a superspeed operation because the low frequency oscillation is suppressed.

摘要翻译： 一种化合物半导体集成电路，具有由作为杂质添加氧的化合物半导体构成的高电阻层和形成在半绝缘性基板和场效应晶体管之间的未掺杂化合物半导体层，所述半导体集成电路从半绝缘性 由于低频振荡被抑制，基板侧适合于超速操作。

公开(公告)号：US5523593A

公开(公告)日：1996-06-04

申请号：US36787

申请日：1993-03-25

申请人： Osamu Kagaya ,  Hiroyuki Takazawa ,  Yoshinori Imamura ,  Junji Shigeta ,  Yukihiro Kawata ,  Hiroto Oda

发明人： Osamu Kagaya ,  Hiroyuki Takazawa ,  Yoshinori Imamura ,  Junji Shigeta ,  Yukihiro Kawata ,  Hiroto Oda

IPC分类号： H01L27/06 ,  H01L29/08 ,  H01L29/778 ,  H01L31/0352

CPC分类号： H01L27/0605 ,  H01L29/0891

摘要： By forming an isolated semiconductor layer or electrode layer on a semiconductor surface between neighboring field effect transistors and element separating trenches which are deep enough to reach at least the semi-insulating substrate or the hetero junction interface on the buffer layer, low frequency oscillation of a compound semiconductor integrated circuit can be reduced. By controlling the thickness of the buffer layer having a hetero junction to at most 150 nm, the low frequency oscillation can be reduced. By forming materials separating adjacent elements with a width of at most 2 .mu.m which reach from the element region surface to the buffer layer having hetero junction so as to enclose the element regions and etched regions in the neighborhood of the elements or so as to enclose the element regions in the etched regions and by controlling the angle of the sides of the etched regions against the semiconductor layer surface to 10.degree. to 60.degree., wires can be prevented from short-circuiting.

摘要翻译： 通过在相邻的场效应晶体管和元件分离沟槽之间的半导体表面上形成隔离的半导体层或电极层，该沟槽深度足以到达缓冲层上的至少半绝缘衬底或异质结界面， 可以减少复合半导体集成电路。 通过将具有异质结的缓冲层的厚度控制为至多150nm，可以降低低频振荡。 通过形成将从元件区域表面到达具有异质结的缓冲层到达的至多2μm的宽度的相邻元件分开形成材料，以便在元件附近包围元件区域和蚀刻区域，以便包围 蚀刻区域中的元件区域和通过将蚀刻区域的侧面相对于半导体层表面的角度控制在10°至60°，可以防止导线短路。