公开(公告)号：US06560674B1

公开(公告)日：2003-05-06

申请号：US09172646

申请日：1998-10-14

申请人： Koji Hosogi ,  Gregorio Gervasio ,  Yatin Mundkur ,  Radhika Thekkath

发明人： Koji Hosogi ,  Gregorio Gervasio ,  Yatin Mundkur ,  Radhika Thekkath

IPC分类号： G06F1200

CPC分类号： G06F12/0835 ,  G06F12/0833 ,  G06F12/0875

摘要： An information processing system has a plurality of modules, including a processor, a main memory and a plurality of I/O devices. A data cache comprises a cache data memory which is coupled to the processor which provides data to the processor in response to a load operation and for writing data from the processor in response to a store operation. A refill controller is coupled to the cache data memory for controlling the operation of the data cache in accordance with a specifiable policy. An external access controller is coupled to the cache data memory. The external access controller is coupled to an external memory bus, such that the contents of the cache data memory are accessible for read and write operations in response to read and write requests issued by the modules in the information processing system.

公开(公告)号：US08125059B2

公开(公告)日：2012-02-28

申请号：US12608307

申请日：2009-10-29

申请人： Kiyoto Ito ,  Koji Hosogi ,  Takanobu Tsunoda

发明人： Kiyoto Ito ,  Koji Hosogi ,  Takanobu Tsunoda

IPC分类号： H01L23/552

CPC分类号： H01L25/0657 ,  H01L2225/06527 ,  H01L2225/06572 ,  H01L2924/0002 ,  H01L2924/00

摘要： A highly flexible semiconductor device of a stacked-type semiconductor device which transfers information by inductive coupling between inductors, in which LSI chips can be stacked even when a transmitter circuit and a receiver circuit are arranged at different positions from each other when viewed in a stacking direction. The semiconductor device has an interposer including a first inductor which is inductively coupled with a transmitter circuit of a first LSI chip to be stacked, and a second inductor which is inductively coupled with a receiver circuit of a second LSI chip to be stacked, the first inductor and the second inductor being electrically connected. An interchip communication is made from the first LSI chip to the second LSI chip.

摘要翻译： 层叠型半导体装置的高度柔性的半导体装置，其通过电感器之间的电感耦合传送信息，即使当发送器电路和接收器电路在堆叠中观察时彼此不同的位置被布置时，也可以堆叠LSI芯片 方向。 半导体器件具有内插器，其包括与要堆叠的第一LSI芯片的发射器电路电感耦合的第一电感器和与要堆叠的第二LSI芯片的接收器电路感应耦合的第二电感器，第一电感器 电感器和第二电感器电连接。 从第一LSI芯片到第二LSI芯片进行芯片间通信。

公开(公告)号：US20080294878A1

公开(公告)日：2008-11-27

申请号：US12101437

申请日：2008-04-11

申请人： Takafumi YUASA ,  Hiroaki Nakata ,  Koji Hosogi ,  Masakazu Ehama ,  Fumitaka Izuhara ,  Kazushi Akie

发明人： Takafumi YUASA ,  Hiroaki Nakata ,  Koji Hosogi ,  Masakazu Ehama ,  Fumitaka Izuhara ,  Kazushi Akie

IPC分类号： G06F9/38 ,  G06F9/302 ,  G06F9/312

CPC分类号： G06F11/0793 ,  G06F9/30054 ,  G06F9/3861 ,  G06F9/3885 ,  G06F9/4812 ,  G06F11/0721 ,  G06F2209/481

摘要： When an error is detected in an error detecting unit in a processor system, the error detecting unit outputs an error signal to an interrupt control unit, and the interrupt control unit outputs a value of an error address register and a control signal to a program counter control unit and rewrites a value of a program counter to a value of an error address register. By this means, the branching process by an error interrupt is realized. In this case, when the error is detected, the process of saving the value of the program counter at the time of error occurrence is not performed, and a specific save register and a control circuit for the recovery to the address at the time of the error occurrence after the end of the error processing are not provided.

摘要翻译： 当在处理器系统中的错误检测单元中检测到错误时，错误检测单元向中断控制单元输出错误信号，并且中断控制单元向程序计数器输出错误地址寄存器和控制信号的值 控制单元，并将程序计数器的值重写为错误地址寄存器的值。 通过这种方式，实现了通过错误中断的分支过程。 在这种情况下，当检测到错误时，不执行在发生错误时保存程序计数器的值的处理，以及特定的存储寄存器和控制电路，用于恢复到发生错误时的地址 未提供错误处理结束后的错误发生。

公开(公告)号：US07177996B2

公开(公告)日：2007-02-13

申请号：US10801834

申请日：2004-03-17

申请人： Masakazu Ehama ,  Kazuhiko Tanaka ,  Koji Hosogi ,  Hiroaki Nakata

发明人： Masakazu Ehama ,  Kazuhiko Tanaka ,  Koji Hosogi ,  Hiroaki Nakata

IPC分类号： G06F12/00

CPC分类号： G06F12/1441 ,  G06F12/1027 ,  G06F12/1425

摘要： Security threats are reduced by providing a TLB in a bus interface unit of a media processor whose contents can be updated only from inside the media processor. The TLB checks whether an address specified by an external access request falls within access-permitted areas registered in it. If it does, an access request from outside is passed on to an inside of the media processor; otherwise, it is rejected.

摘要翻译： 通过在媒体处理器的总线接口单元中提供TLB来减少安全威胁，其媒体处理器的内容可以仅从媒体处理器内部更新。 TLB检查由外部访问请求指定的地址是否落在其中注册的访问允许区域内。 如果是这样，则来自外部的访问请求被传递到媒体处理器的内部; 否则就被拒绝。

公开(公告)号：US20110096879A1

公开(公告)日：2011-04-28

申请号：US13002324

申请日：2009-06-26

申请人： Masakazu Ehama ,  Koji Hosogi

发明人： Masakazu Ehama ,  Koji Hosogi

IPC分类号： H04B1/10 ,  G06F17/10

CPC分类号： H03H17/0294 ,  H04N19/117 ,  H04N19/42 ,  H04N19/523 ,  H04N19/80

摘要： The present invention provides a technique for changing the number of taps in filter processing without the need for execution of branch processing. A filter processing device comprises: an arithmetic circuit that performs arithmetic processing for filtering operation; an internal register that retains data to be subjected to arithmetic processing in the arithmetic circuit and that receives the result of arithmetic processing from the arithmetic circuit as data to be written back thereto; and a data generator that generates data to be fed to the arithmetic circuit through use of the data retained in the internal register. Further, in the filter processing device, there is disposed a tap number control circuit that is capable of controlling the number of taps in filter processing according to a tap control signal applied thereto. In this configuration, no branch processing is required for controlling the number of taps by the use of the tap number control circuit.

摘要翻译： 本发明提供了一种用于在不需要执行分支处理的情况下改变滤波处理中的抽头数量的技术。 一种滤波处理装置，包括：运算电路，进行滤波运算的运算处理; 内部寄存器，其保留在运算电路中进行算术处理的数据，并从运算电路接收运算结果的结果作为要被写回的数据; 以及数据生成器，其通过使用保持在内部寄存器中的数据来生成要馈送到运算电路的数据。 此外，在滤波处理装置中，设置有能够根据施加到其上的抽头控制信号来控制滤波处理中的抽头数的抽头号控制电路。 在这种配置中，通过使用抽头数控制电路来控制抽头数目不需要分支处理。

公开(公告)号：US20100146234A1

公开(公告)日：2010-06-10

申请号：US12706285

申请日：2010-02-16

申请人： Masakazu EHAMA ,  Kazuhiko Tanaka ,  Koji Hosogi ,  Hiroaki Nakata

发明人： Masakazu EHAMA ,  Kazuhiko Tanaka ,  Koji Hosogi ,  Hiroaki Nakata

IPC分类号： G06F12/14 ,  G06F12/00 ,  G06F13/14

CPC分类号： G06F12/1441 ,  G06F12/1027 ,  G06F12/1425

摘要： An external bus interface method including: receiving, via an access control unit, an access request conveyed through an external bus, and judging, via an access judging unit connected to the access control unit, whether the access request is to be honored or rejected, wherein upon receiving the access request, the access control unit sends to the access judging unit an access judging check request signal asking whether the requested address falls within one of access-permitted areas registered in the access judging unit, the access judging unit checks whether the requested address falls within one of the access-permitted areas registered in it and returns to the access control unit, an access judging check result signal indicating whether the access request is to be honored or rejected, and if the access judging check result signal indicates that the access request is to be rejected, the access control unit nullifies the access request.

摘要翻译： 一种外部总线接口方法，包括：经由访问控制单元接收通过外部总线传送的访问请求，并且经由与所述访问控制单元连接的访问​​判断单元判断所述访问请求是否被履行或拒绝， 其中，在接收到所述访问请求时，所述访问控制单元向所述访问判断单元发送访问判断检查请求信号，询问所请求的地址是否落入在所述访问判断单元中登记的访问允许区域之一内，所述访问判断单元检查是否 所请求的地址落在登记在其中的访问许可区域之一内，并返回到访问控制单元，指示是否要访问或拒绝访问请求的访问判断检查结果信号，以及访问判断检查结果信号是否指示 访问请求将被拒绝，访问控制单元使访问请求无效。

公开(公告)号：US07664925B2

公开(公告)日：2010-02-16

申请号：US12258685

申请日：2008-10-27

申请人： Masakazu Ehama ,  Kazuhiko Tanaka ,  Koji Hosogi ,  Hiroaki Nakata

发明人： Masakazu Ehama ,  Kazuhiko Tanaka ,  Koji Hosogi ,  Hiroaki Nakata

IPC分类号： G06F12/00

CPC分类号： G06F12/1441 ,  G06F12/1027 ,  G06F12/1425

摘要： Access control unit sends to the access judging unit an access judging check request signal asking whether the requested address falls within one of the access-permitted areas registered in the access judging unit, the access judging unit checks whether the requested address falls within one of the access-permitted areas registered in it and returns to the access control unit an access judging check result signal indicating whether the access request is to be honored or rejected, and the access control unit permits access to the internal bus if the access judging check result signal indicates that the access request is to be honored, or rejects the access request otherwise.

摘要翻译： 访问控制单元向访问判断单元发送访问判断检查请求信号，询问所请求的地址是否落在在访问判断单元中登记的访问允许区域之一内，访问判断单元检查请求的地址是否落入 在其中登记的访问许可区域，并且返回到访问控制单元的访问判断检查结果信号，该访问判断检查结果信号指示访问请求是否被遵从或拒绝，并且如果访问判断检查结果信号则访问控制单元允许访问内部总线 表示要访问访问请求，否则拒绝访问请求。

公开(公告)号：US08957883B2

公开(公告)日：2015-02-17

申请号：US12844923

申请日：2010-07-28

申请人： Junichi Maruyama ,  Koji Hosogi ,  Goki Toshima ,  Misa Owa ,  Naruhiko Kasai ,  Kikuo Ono

发明人： Junichi Maruyama ,  Koji Hosogi ,  Goki Toshima ,  Misa Owa ,  Naruhiko Kasai ,  Kikuo Ono

IPC分类号： G06F3/00 ,  G09G5/00 ,  G09G3/20 ,  G09G3/36

CPC分类号： G09G3/2096 ,  G09G3/3666 ,  G09G2310/0221 ,  G09G2310/04 ,  G09G2320/0247 ,  G09G2320/10 ,  G09G2330/021 ,  G09G2340/0435

摘要： A display device includes a frame frequency conversion circuit configured to convert a frame frequency of an input display data and a timing control circuit configured to control a first drive circuit and a second drive circuit based on a frame frequency after the conversion. The display device generates at least two display areas on the display panel. The at least two display areas display images at different frame frequencies. The display device further includes a switch unit configured to display an image at the frame frequency before the conversion at one of the at least two display areas and configured to display an image at the frame frequency after the conversion at another one of the at least two display areas. At least one of a boundary position and a size of the at least two display areas varies with time.

摘要翻译： 显示装置包括：帧频转换电路，被配置为转换输入显示数据的帧频;以及定时控制电路，被配置为基于转换后的帧频控制第一驱动电路和第二驱动电路。 显示装置在显示面板上产生至少两个显示区域。 至少两个显示区域以不同的帧频显示图像。 所述显示装置还包括：开关单元，被配置为在所述至少两个显示区域之一处的所述转换之前以帧频显示图像，并且被配置为在所述至少两个显示区域中的另一个上转换之后以帧频率显示图像 显示区域。 至少两个显示区域的边界位置和尺寸中的至少一个随着时间而变化。

公开(公告)号：US08310437B2

公开(公告)日：2012-11-13

申请号：US12625655

申请日：2009-11-25

申请人： Junichi Maruyama ,  Koji Hosogi ,  Yoshihisa Ooishi ,  Misa Owa ,  Kikuo Ono

发明人： Junichi Maruyama ,  Koji Hosogi ,  Yoshihisa Ooishi ,  Misa Owa ,  Kikuo Ono

IPC分类号： G09G3/36

CPC分类号： G09G3/3426 ,  G02F1/133603 ,  G09G3/3413 ,  G09G2310/024 ,  G09G2320/0242 ,  G09G2320/0247 ,  G09G2320/0261 ,  G09G2320/0606 ,  G09G2320/0633 ,  G09G2320/064 ,  G09G2320/0666 ,  G09G2320/103 ,  G09G2330/02 ,  G09G2330/021 ,  G09G2360/16

摘要： The backlight device includes: a backlight including a plurality of light sources; and a backlight control part. The backlight includes a plurality of divided areas, and light sources disposed in each of the plurality of divided areas are chain-connected. The backlight control part includes at least one backlight control unit for controlling turning on and off of the backlight which includes the plurality of divided areas, with respect to the each divided area. The backlight control unit includes a selection unit for selecting one of divided areas, at least one backlight drive path. The selection unit selects the one of divided areas in a time division manner, and the light sources of the one of divided areas are driven by sharing the at least one backlight drive path in common.

摘要翻译： 背光装置包括：背光源，包括多个光源; 和背光控制部。 背光源包括多个分割区域，并且配置在多个分割区域的每一个中的光源链接。 背光控制部分包括至少一个背光控制单元，用于相对于每个划分的区域控制包括多个划分区域的背光源的导通和关闭。 背光控制单元包括：选择单元，用于选择分割区域中的一个，至少一个背光驱动路径。 选择单元以时分方式选择分割区域中的一个，并且通过共享至少一个背光驱动路径来驱动分割区域中的一个的光源。

公开(公告)号：US20120263233A1

公开(公告)日：2012-10-18

申请号：US13533570

申请日：2012-06-26

申请人： Kenichi IWATA ,  Seiji Mochizuki ,  Tetsuya Shibayama ,  Fumitaka Izuhara ,  Hiroshi Ueda ,  Yukifumi Kobayashi ,  Hiroaki Nakata ,  Koji Hosogi ,  Masakazu Ehama ,  Takafumi Yuasa

发明人： Kenichi IWATA ,  Seiji Mochizuki ,  Tetsuya Shibayama ,  Fumitaka Izuhara ,  Hiroshi Ueda ,  Yukifumi Kobayashi ,  Hiroaki Nakata ,  Koji Hosogi ,  Masakazu Ehama ,  Takafumi Yuasa

IPC分类号： H04N7/26 ,  H04N7/32

CPC分类号： H04N19/436 ,  H04N19/176 ,  H04N19/593

摘要： The present invention provides a functional block that executes video coding and video decoding based on H. 264/AVC. The functional block includes two moving picture processing units, and a memory unit that stores therein data related to the results of processing of first plural macroblocks arranged within one row of one picture by the first moving picture processing unit. Data related to the results of processing of plural adjacent macroblocks, which are selected from the data stored in the memory unit, are transferred to the second moving picture processing unit. The second moving picture processing unit performs processing of one macroblock of second plural macroblocks arranged in the following row, using the transferred data.

摘要翻译： 本发明提供一种执行基于H.264 / AVC的视频编码和视频解码的功能块。 功能块包括两个运动图像处理单元，以及存储单元，其存储与第一运动图像处理单元一行布置在一行内的第一多个宏块的处理结果有关的数据。 与从存储在存储单元中的数据中选择的多个相邻宏块的处理结果有关的数据被传送到第二运动图像处理单元。 第二运动图像处理单元使用传送的数据来执行排列在下一行中的第二多个宏块的一个宏块的处理。