公开(公告)号：US5416740A

公开(公告)日：1995-05-16

申请号：US987757

申请日：1992-12-09

申请人： Koreaki Fujita ,  Masayuki Yamashita ,  Masamitsu Shimasaki

发明人： Koreaki Fujita ,  Masayuki Yamashita ,  Masamitsu Shimasaki

IPC分类号： G11C11/413 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G11C29/44 ,  G11C7/00

CPC分类号： G11C29/808 ,  G11C29/44

摘要： An SRAM disclosed herein includes 64 memory cell array blocks and a redundant memory cell array block. The redundant memory cell array includes a total of 16 redundant memory cell columns. A defect address indicating a location of a defective memory column is programmed in an address programming circuit, and the specific defecting column in the defect address is programmed in an I/O programming circuit. Although each memory cell does not include a spare memory cell column or row for redundancy, the defect can be repaired by using a redundant memory cell array, so that the high integration of the SRAM can be accomplished.

摘要翻译： 本文公开的SRAM包括64个存储单元阵列块和冗余存储单元阵列块。 冗余存储单元阵列包括总共16个冗余存储单元列。 指示缺陷存储器列的位置的缺陷地址被编程在地址编程电路中，缺陷地址中的特定缺陷列被编程在I / O编程电路中。 虽然每个存储器单元不包括用于冗余的备用存储单元列或行，但是可以通过使用冗余存储单元阵列来修复缺陷，使得可以实现SRAM的高集成度。

公开(公告)号：US5612917A

公开(公告)日：1997-03-18

申请号：US417171

申请日：1995-04-05

申请人： Kunihiko Kozaru ,  Koreaki Fujita

发明人： Kunihiko Kozaru ,  Koreaki Fujita

IPC分类号： G11C11/413 ,  G11C11/401 ,  G11C11/407 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC分类号： G11C29/84 ,  G11C29/781

摘要： A dynamic random access memory includes memory cell array blocks, row decoders, redundant word lines, redundant memory cells, replacement circuits, and a normal memory cell de-select circuit. Each memory cell array block includes normal word lines and normal memory cells. Each row decoder is provided corresponding to one memory cell array block. Any of the redundant word line is provided corresponding to one memory cell array block. Each replacement circuit includes a redundancy select circuit, a replacement address program circuit, and a redundant word line select circuit. The redundancy select circuit has set in advance whether a corresponding redundant word line is to be used or not. The program circuit has an address programmed of a normal word line to be replaced with a corresponding redundant word line. The normal memory cell de-select circuit inactivates a row decoder in response to an output of the replacement circuit when any replacement circuit selects a corresponding redundant word line. When a corresponding redundant word line is not used, a predecode signal is distributed to a program circuit so that the loads of a predecode signal are equal to each other.

摘要翻译： 动态随机存取存储器包括存储单元阵列块，行解码器，冗余字线，冗余存储单元，替换电路和正常存储单元去选电路。 每个存储单元阵列块包括普通字线和正常存储器单元。 相应于一个存储单元阵列块提供每行解码器。 对应于一个存储单元阵列块提供任何冗余字线。 每个替换电路包括冗余选择电路，替换地址程序电路和冗余字线选择电路。 预先设置了冗余选择电路，是否使用对应的冗余字线。 程序电路具有用相应的冗余字线代替的正常字线编程的地址。 当任何替换电路选择相应的冗余字线时，正常存储单元去选择电路响应于替换电路的输出而使行解码器失活。 当不使用对应的冗余字线时，将预解码信号分配给程序电路，使得预解码信号的负载彼此相等。

公开(公告)号：US5282175A

公开(公告)日：1994-01-25

申请号：US705817

申请日：1991-05-24

申请人： Koreaki Fujita ,  Shuji Murakami ,  Kenji Anami

发明人： Koreaki Fujita ,  Shuji Murakami ,  Kenji Anami

IPC分类号： G11C11/418 ,  G11C8/12 ,  G11C8/14 ,  G11C11/401 ,  G11C11/407 ,  G11C11/41

CPC分类号： G11C8/14 ,  G11C8/12

摘要： In a SRAM of a selected word line structure, each local decoder is connected to a corresponding main word line and a corresponding Z decoder signal line. Each local decoder includes a circuit including two MOS transistors connected in series to each other which circuit has one end grounded. The corresponding local word line is connected to a node between these two transistors. Out of the corresponding main word line and the corresponding Z decoder signal line, one is connected to the gates of these transistors and the other is connected to the other end of said circuit, which the other end is not grounded. The potential on the corresponding local word line attains a high level only when the potential on the signal line connected to the gate of these two transistors, is at a logical level at which the transistor can be turned on and the potential on said one signal line is at a high level. Theoretically, therefore, each local word line is controlled to be activated or inactivated by the operations of two elements in the corresponding local decoder.

摘要翻译： 在所选字线结构的SRAM中，每个本地解码器连接到对应的主字线和对应的Z解码器信号线。 每个本地解码器包括一个包括彼此串联连接的两个MOS晶体管的电路，该电路具有一端接地。 相应的本地字线连接到这两个晶体管之间的节点。 在相应的主字线和相应的Z解码器信号线之外，一个连接到这些晶体管的栅极，另一个连接到另一端不接地的所述电路的另一端。 只有当连接到这两个晶体管的栅极的信号线上的电位处于晶体管可以导通的逻辑电平并且所述一个信号线上的电位时，相应本地字线上的电位才达到高电平 处于高水平。 因此，理论上，每个局部字线被相应的本地解码器中的两个元件的操作控制为被激活或失活。

公开(公告)号：US4767942A

公开(公告)日：1988-08-30

申请号：US46509

申请日：1987-05-06

申请人： Hiroshi Minami ,  Koreaki Fujita

发明人： Hiroshi Minami ,  Koreaki Fujita

IPC分类号： H03K5/02 ,  H03F3/45 ,  H03K3/3565 ,  H03K5/08 ,  H03K17/04 ,  H03K17/687 ,  H03K3/01 ,  H03F3/04 ,  H03K3/353

CPC分类号： H03F3/45179 ,  H03K3/3565 ,  H03F2203/45364 ,  H03F2203/45394 ,  H03F2203/45674 ,  H03F2203/45712

摘要： In a MOS transistor circuit (comprising a pair of current mirror circuits, each comprising: first and second MOS transistors having their gate electrodes connected together; third and fourth MOS transistors respectively connected in series with the first and second transistors the third and the fourth MOS transistors of the pair of current mirror circuits receiving a pair of complementary signals at their gate electrodes; and the nodes between the second and the fourth MOS transistors forming output nodes of the current mirror circuits), a pair of capacitors each coupling the output of one current mirror circuit to the gate electrodes of the first and the second MOS transistors of the other current mirror circuit. This provides positive feedback. The change in the outputs responsive to change in the inputs is thereby accelerated.

摘要翻译： 在MOS晶体管电路（包括一对电流镜电路）中，每一个包括：第一和第二MOS晶体管，其栅电极连接在一起;第三和第四MOS晶体管分别与第一和第二晶体管串联连接，第三和第四MOS晶体管 一对电流镜电路的晶体管在其栅电极处接收一对互补信号;以及形成电流镜电路的输出节点的第二MOS晶体管和第四MOS晶体管之间的节点），一对电容器，其将一个 电流镜电路连接到另一电流镜电路的第一和第二MOS晶体管的栅电极。 这提供了积极的反馈。 因此，响应于输入变化的输出的变化被加速。

公开(公告)号：US5446692A

公开(公告)日：1995-08-29

申请号：US8109

申请日：1993-01-25

申请人： Yoshiyuki Haraguchi ,  Koreaki Fujita ,  Kiyoyasu Akai

发明人： Yoshiyuki Haraguchi ,  Koreaki Fujita ,  Kiyoyasu Akai

IPC分类号： G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G11C13/00

CPC分类号： G11C29/808 ,  G11C29/781

摘要： An improved SRAM is disclosed including a plurality of memory blocks each having a redundancy memory cell to be shared. In redundancy row decoders 50a, 50b, 50c provided in each memory block, a memory block to be remedied is programmed. Accordingly, a redundancy memory cell row corresponding to each redundancy row decoder can be used for remedy of a defect memory cell in another memory block. Since a defect memory cell may be remedied flexibly, the yield rate in production of semiconductor memories is improved.

摘要翻译： 公开了一种改进的SRAM，其包括多个存储块，每个存储块具有要共享的冗余存储单元。 在设置在每个存储器块中的冗余行解码器50a，50b，50c中，对待补救的存储块进行编程。 因此，对应于每个冗余行解码器的冗余存储单元行可用于补救另一个存储块中的缺陷存储单元。 由于可以灵活地补救缺陷存储单元，所以提高了半导体存储器的生产中的成品率。

公开(公告)号：US5392247A

公开(公告)日：1995-02-21

申请号：US254448

申请日：1994-06-06

申请人： Koreaki Fujita

发明人： Koreaki Fujita

IPC分类号： G11C29/00 ,  G11C7/00 ,  G06F11/00 ,  G11C8/00

CPC分类号： G11C29/808

摘要： An addressing system of redundancy word lines is provided independently of an addressing system of word lines in memory cell array blocks. Outputs of substitution circuits including redundancy selecting circuits and substitute address program circuits are applied as redundancy word line activating signals directly to the redundancy word lines not through decoders, respectively. An output of a normal memory cell nonselecting circuit is applied as a decoder inactivating signal to the decoders.

摘要翻译： 与存储单元阵列块中的字线的寻址系统无关地提供冗余字线的寻址系统。 包括冗余选择电路和替代地址编程电路的替换电路的输出分别作为冗余字线激活信号直接应用于冗余字线，而不是通过解码器。 将正常存储单元非选择电路的输出作为解码器失活信号施加到解码器。

公开(公告)号：US5379259A

公开(公告)日：1995-01-03

申请号：US24141

申请日：1993-03-01

申请人： Koreaki Fujita

发明人： Koreaki Fujita

IPC分类号： G11C11/413 ,  G11C11/401 ,  G11C11/407 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC分类号： G11C29/808

摘要： Two redundant blocks RB1 and RB2 are provided independent from the normal memory cell block BL, and selection of the redundant block when redundancy is selected is carried out by a least significant column address signal Y0 and a signal /Y0 complementary thereto in a semiconductor memory device. Therefore, a semiconductor memory device can be provided in which when defective bits exist continuously in a memory cell array, the continuous defective bit can be replaced by two redundant bit lines.

摘要翻译： 独立于正常存储器单元块BL提供两个冗余块RB1和RB2，并且当选择冗余时的冗余块的选择由半导体存储器件中的最低有效列地址信号Y0和与其互补的信号/ Y0执行 。 因此，可以提供半导体存储器件，其中当存储单元阵列中连续存在有缺陷的位时，连续的有缺陷的位可被两个冗余的位线替代。

公开(公告)号：US5063305A

公开(公告)日：1991-11-05

申请号：US338896

申请日：1989-04-14

申请人： Hiroshi Minami ,  Koreaki Fujita

发明人： Hiroshi Minami ,  Koreaki Fujita

IPC分类号： H03F3/45 ,  H03K3/3565

CPC分类号： H03K3/3565 ,  H03F3/45076 ,  H03F3/45179 ,  H03F2203/45364 ,  H03F2203/45394 ,  H03F2203/45674 ,  H03F2203/45712

摘要： In a MOS transistor circuit (comprising a pair of current mirror circuits, each comprising: first and second MOS transistors having their gate electrodes connected together third and fourth MOS transistors respectively connected in series with the first and second transistors, the third and the fourth MOS transistors of the pair of current mirror circuits receiving a pair of complementary signals at their gate electrodes; and the nodes between the second and the fourth MOS transistors forming output nodes of the current mirror circuits), a pair of capacitors each coupling the output of one current mirror circuit to the gate electrodes of the first and the second MOS transistors of the other current mirror circuit. This provides positive feedback. The change in the outputs responsive to change in the inputs is thereby accelerated.

公开(公告)号：US4907201A

公开(公告)日：1990-03-06

申请号：US218888

申请日：1988-07-14

申请人： Hiroshi Minami ,  Koreaki Fujita

发明人： Hiroshi Minami ,  Koreaki Fujita

IPC分类号： H03F3/45 ,  H03K3/3565

CPC分类号： H03K3/3565 ,  H03F3/45076 ,  H03F3/45179 ,  H03F2203/45364 ,  H03F2203/45394 ,  H03F2203/45674 ,  H03F2203/45712

摘要： In a MOS transistor circuit (comprising a pair of current mirror circuits, each comprising: first and second MOS transistors having their gate electrodes connected together third and fourth MOS transistors respectively connected in series with the first and second transistors, the third and the fourth MOS transistors of the pair of current mirror circuits receiving a pair of complementary signals at their gate electrodes; and the nodes between the second and the fourth MOS transistors forming output nodes of the current mirror circuit), a pair of capacitors each coupling the output of one current mirror circuit to the gate electrodes of the first and the second MOS transistors of the other current mirror circuit. This provides positive feedback. The change in the outputs responsive to change in the inputs is thereby accelerated.

摘要翻译： 在MOS晶体管电路（包括一对电流镜电路）中，每一个包括：第一和第二MOS晶体管，其栅电极连接在一起分别与第一和第二晶体管串联的第三和第四MOS晶体管，第三和第四MOS 一对电流镜电路的晶体管在其栅电极处接收一对互补信号;以及第二和第四MOS晶体管之间的节点，形成电流镜电路的输出节点），一对电容器，每个电容器将一个 电流镜电路连接到另一电流镜电路的第一和第二MOS晶体管的栅电极。 这提供了积极的反馈。 因此，响应于输入变化的输出的变化被加速。