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公开(公告)号：US07937633B2
公开(公告)日：2011-05-03
申请号：US12190196
申请日：2008-08-12
IPC分类号： G11C29/00
CPC分类号： G11C29/48 , G11C29/56012 , G11C2029/0401 , G11C2029/5602 , H01L2924/0002 , H01L2924/00
摘要： A system-in-package type semiconductor device includes a logic chip; and a memory chip connected with external terminal through the logic chip. The logic chip includes a data holding circuit configured to hold a test data in a test mode, and store the test data supplied through the data input/output terminal in the data holding circuit in response to a test data set command, and writes the test data which has been stored in the data holding circuit in the memory chip in response to the test data write command.
摘要翻译： 系统级封装型半导体器件包括逻辑芯片; 以及通过逻辑芯片与外部端子连接的存储芯片。 逻辑芯片包括：数据保持电路，被配置为将测试数据保存在测试模式中，并且响应于测试数据设置命令将通过数据输入/输出端子提供的测试数据存储在数据保持电路中，并且将测试 响应于测试数据写入命令已经存储在存储器芯片中的数据保持电路中的数据。
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公开(公告)号：US20090049349A1
公开(公告)日：2009-02-19
申请号：US12190196
申请日：2008-08-12
CPC分类号： G11C29/48 , G11C29/56012 , G11C2029/0401 , G11C2029/5602 , H01L2924/0002 , H01L2924/00
摘要： A system-in-package type semiconductor device includes a logic chip; and a memory chip connected with external terminal through the logic chip. The logic chip includes a data holding circuit configured to hold a test data in a test mode, and store the test data supplied through the data input/output terminal in the data holding circuit in response to a test data set command, and writes the test data which has been stored in the data holding circuit in the memory chip in response to the test data write command.
摘要翻译： 系统级封装型半导体器件包括逻辑芯片; 以及通过逻辑芯片与外部端子连接的存储芯片。 逻辑芯片包括：数据保持电路，被配置为将测试数据保存在测试模式中，并且响应于测试数据设置命令将通过数据输入/输出端子提供的测试数据存储在数据保持电路中，并且将测试 响应于测试数据写入命令已经存储在存储器芯片中的数据保持电路中的数据。
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公开(公告)号：US20090190417A1
公开(公告)日：2009-07-30
申请号：US12350546
申请日：2009-01-08
CPC分类号： G11C29/14 , G11C11/401 , G11C29/12015 , G11C29/56012
摘要： A semiconductor integrated circuit device includes a first chip that is directly accessible from outside, a second chip that transmits and receives data to and from the first chip, the second chip being not directly accessible from outside, and a through circuit that is provided in the first chip and transmits first and second test signals input from an external device to the second chip, wherein the through circuit includes a first signal transmission path to generate a first signal by synchronizing the first test signal to a clock signal input from the external device and to output it to the second chip and a second signal transmission path to generate a second signal by synchronizing the second test signal to a test clock signal input from the external device and to output it to the second chip.
摘要翻译： 半导体集成电路器件包括可从外部直接访问的第一芯片，向第一芯片发送数据和从第一芯片接收数据的第二芯片，第二芯片不能从外部直接访问;以及贯穿电路，其设置在 第一芯片，并将从外部设备输入的第一和第二测试信号传输到第二芯片，其中所述通过电路包括第一信号传输路径，以通过将所述第一测试信号与从所述外部设备输入的时钟信号同步来产生第一信号;以及 将其输出到第二芯片和第二信号传输路径，以通过将第二测试信号与从外部设备输入的测试时钟信号同步并将其输出到第二芯片来产生第二信号。
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公开(公告)号：US07965568B2
公开(公告)日：2011-06-21
申请号：US12350546
申请日：2009-01-08
IPC分类号： G11C7/00
CPC分类号： G11C29/14 , G11C11/401 , G11C29/12015 , G11C29/56012
摘要： A semiconductor integrated circuit device includes a first chip that is directly accessible from outside, a second chip that transmits and receives data to and from the first chip, the second chip being not directly accessible from outside, and a through circuit that is provided in the first chip and transmits first and second test signals input from an external device to the second chip, wherein the through circuit includes a first signal transmission path to generate a first signal by synchronizing the first test signal to a clock signal input from the external device and to output it to the second chip and a second signal transmission path to generate a second signal by synchronizing the second test signal to a test clock signal input from the external device and to output it to the second chip.
摘要翻译： 半导体集成电路器件包括可从外部直接访问的第一芯片，向第一芯片发送数据和从第一芯片接收数据的第二芯片，第二芯片不能从外部直接访问;以及贯穿电路，其设置在 第一芯片，并将从外部设备输入的第一和第二测试信号传输到第二芯片，其中所述通过电路包括第一信号传输路径，以通过将所述第一测试信号与从所述外部设备输入的时钟信号同步来产生第一信号;以及 将其输出到第二芯片和第二信号传输路径，以通过将第二测试信号与从外部设备输入的测试时钟信号同步并将其输出到第二芯片来产生第二信号。
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公开(公告)号：US07639554B2
公开(公告)日：2009-12-29
申请号：US12018993
申请日：2008-01-24
IPC分类号： G11C29/00
CPC分类号： G11C29/52 , G11C16/04 , G11C16/3445 , G11C29/26 , G11C29/50004
摘要： A semiconductor device includes: a first memory; and a second memory. The first memory includes: a first memory cell array configured to be divided into a plurality of sectors, an erasure time setting register configured to hold a sector erasure assurance time to assure an erasure time for erasing data stored in one sector, and a first control circuit configured to execute a sector erasure test in which data stored in at least one selected sector selected from the plurality of sectors are erased within the sector erasure assurance time. The second memory includes: a second memory cell array configured to have a data storage system different from that of the first memory cell array, and a second control circuit configured to execute a data hold test with respect to the second memory cell array while the sector erasure test is executed.
摘要翻译： 半导体器件包括：第一存储器; 和第二个记忆。 第一存储器包括：第一存储单元阵列，被配置为被划分为多个扇区;擦除时间设置寄存器，被配置为保持扇区擦除保证时间，以确保用于擦除存储在一个扇区中的数据的擦除时间;以及第一控制 电路，被配置为执行扇区擦除测试，其中存储在从所述多个扇区中选择的至少一个所选扇区中的数据在所述扇区擦除保证时间内被擦除。 第二存储器包括：第二存储单元阵列，被配置为具有与第一存储单元阵列的数据存储系统不同的数据存储系统;以及第二控制电路，被配置为执行相对于第二存储单元阵列的数据保持测试， 执行擦除测试。
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公开(公告)号：US06421277B2
公开(公告)日：2002-07-16
申请号：US09745787
申请日：2000-12-21
申请人： Nobutoshi Tsunesada
发明人： Nobutoshi Tsunesada
IPC分类号： G11C1134
CPC分类号： G11C16/3409 , G11C16/3404 , G11C16/3445
摘要： A threshold voltage distribution D2 apparently decreases to a distribution D3 when there is a distribution D1 of memory cells having deep depletion. After an erase is performed utilizing an erase determination level 1 higher than a desired erase determination level 2, only data in memory cells of distribution D1 is rewritten utilizing a rewrite determination level 1 lower than a desired rewrite determination level 2. The erase is performed utilizing erase determination level 2 since the threshold voltage distribution shifts a distribution D7 by canceling the effect caused by the memory cells having deep depletion, and only data in the memory cells having shallow depletion is rewritten.
摘要翻译： 当存在具有深度耗尽的存储器单元的分布D1时，阈值电压分布D2明显地降低到分布D3。 在使用比期望的擦除判定级别2更高的擦除判定级别1进行擦除之后，仅利用低于期望的重写判定级别2的重写判定级别1来重写分配D1的存储器单元中的数据。利用 因为阈值电压分布通过消除由具有深度耗尽的存储器单元所引起的影响来移动分布D7，并且仅改写具有浅耗散的存储单元中的数据。
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