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公开(公告)号：US20090190417A1
公开(公告)日：2009-07-30
申请号：US12350546
申请日：2009-01-08
CPC分类号： G11C29/14 , G11C11/401 , G11C29/12015 , G11C29/56012
摘要： A semiconductor integrated circuit device includes a first chip that is directly accessible from outside, a second chip that transmits and receives data to and from the first chip, the second chip being not directly accessible from outside, and a through circuit that is provided in the first chip and transmits first and second test signals input from an external device to the second chip, wherein the through circuit includes a first signal transmission path to generate a first signal by synchronizing the first test signal to a clock signal input from the external device and to output it to the second chip and a second signal transmission path to generate a second signal by synchronizing the second test signal to a test clock signal input from the external device and to output it to the second chip.
摘要翻译： 半导体集成电路器件包括可从外部直接访问的第一芯片，向第一芯片发送数据和从第一芯片接收数据的第二芯片，第二芯片不能从外部直接访问;以及贯穿电路，其设置在 第一芯片，并将从外部设备输入的第一和第二测试信号传输到第二芯片，其中所述通过电路包括第一信号传输路径，以通过将所述第一测试信号与从所述外部设备输入的时钟信号同步来产生第一信号;以及 将其输出到第二芯片和第二信号传输路径，以通过将第二测试信号与从外部设备输入的测试时钟信号同步并将其输出到第二芯片来产生第二信号。
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公开(公告)号：US07965568B2
公开(公告)日：2011-06-21
申请号：US12350546
申请日：2009-01-08
IPC分类号： G11C7/00
CPC分类号： G11C29/14 , G11C11/401 , G11C29/12015 , G11C29/56012
摘要： A semiconductor integrated circuit device includes a first chip that is directly accessible from outside, a second chip that transmits and receives data to and from the first chip, the second chip being not directly accessible from outside, and a through circuit that is provided in the first chip and transmits first and second test signals input from an external device to the second chip, wherein the through circuit includes a first signal transmission path to generate a first signal by synchronizing the first test signal to a clock signal input from the external device and to output it to the second chip and a second signal transmission path to generate a second signal by synchronizing the second test signal to a test clock signal input from the external device and to output it to the second chip.
摘要翻译： 半导体集成电路器件包括可从外部直接访问的第一芯片，向第一芯片发送数据和从第一芯片接收数据的第二芯片，第二芯片不能从外部直接访问;以及贯穿电路，其设置在 第一芯片，并将从外部设备输入的第一和第二测试信号传输到第二芯片，其中所述通过电路包括第一信号传输路径，以通过将所述第一测试信号与从所述外部设备输入的时钟信号同步来产生第一信号;以及 将其输出到第二芯片和第二信号传输路径，以通过将第二测试信号与从外部设备输入的测试时钟信号同步并将其输出到第二芯片来产生第二信号。
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公开(公告)号：US07937633B2
公开(公告)日：2011-05-03
申请号：US12190196
申请日：2008-08-12
IPC分类号： G11C29/00
CPC分类号： G11C29/48 , G11C29/56012 , G11C2029/0401 , G11C2029/5602 , H01L2924/0002 , H01L2924/00
摘要： A system-in-package type semiconductor device includes a logic chip; and a memory chip connected with external terminal through the logic chip. The logic chip includes a data holding circuit configured to hold a test data in a test mode, and store the test data supplied through the data input/output terminal in the data holding circuit in response to a test data set command, and writes the test data which has been stored in the data holding circuit in the memory chip in response to the test data write command.
摘要翻译： 系统级封装型半导体器件包括逻辑芯片; 以及通过逻辑芯片与外部端子连接的存储芯片。 逻辑芯片包括：数据保持电路，被配置为将测试数据保存在测试模式中，并且响应于测试数据设置命令将通过数据输入/输出端子提供的测试数据存储在数据保持电路中，并且将测试 响应于测试数据写入命令已经存储在存储器芯片中的数据保持电路中的数据。
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公开(公告)号：US20090049349A1
公开(公告)日：2009-02-19
申请号：US12190196
申请日：2008-08-12
CPC分类号： G11C29/48 , G11C29/56012 , G11C2029/0401 , G11C2029/5602 , H01L2924/0002 , H01L2924/00
摘要： A system-in-package type semiconductor device includes a logic chip; and a memory chip connected with external terminal through the logic chip. The logic chip includes a data holding circuit configured to hold a test data in a test mode, and store the test data supplied through the data input/output terminal in the data holding circuit in response to a test data set command, and writes the test data which has been stored in the data holding circuit in the memory chip in response to the test data write command.
摘要翻译： 系统级封装型半导体器件包括逻辑芯片; 以及通过逻辑芯片与外部端子连接的存储芯片。 逻辑芯片包括：数据保持电路，被配置为将测试数据保存在测试模式中，并且响应于测试数据设置命令将通过数据输入/输出端子提供的测试数据存储在数据保持电路中，并且将测试 响应于测试数据写入命令已经存储在存储器芯片中的数据保持电路中的数据。
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公开(公告)号：US20050047239A1
公开(公告)日：2005-03-03
申请号：US10500400
申请日：2002-12-25
申请人： Hiroyuki Takahashi , Takuya Hirota , Noriaki Komatsu , Atsushi Nakagawa , Susumu Takano , Masahiro Yoshida , Yuuji Torige , Hideo Inaba
发明人： Hiroyuki Takahashi , Takuya Hirota , Noriaki Komatsu , Atsushi Nakagawa , Susumu Takano , Masahiro Yoshida , Yuuji Torige , Hideo Inaba
IPC分类号： G11C11/403 , G11C11/406 , G11C7/00
CPC分类号： G11C11/40603 , G11C11/406
摘要： Refresh of memory cells is performed periodically by a refresh timer, and collision between memory access and memory refresh is avoided. When memory access occurs, an F/F 163 is set by a one shot pulse from an OS circuit 161, a memory access request is inputted to a memory accessing pulse generator circuit 171 through a NOR gate 167, and a latch control signal LC and an enable signal REN are outputted. When a refresh request from the refresh timer is inputted to an AND gate 168 during the memory access, the output of the NOR gate 167 is at the “L” level, and the refresh request is blocked by the AND gate 168. Thereafter, at the time when the latch control signal LC is turned into the “L” level, F/Fs 163, 164 and 165 are reset, the output of the NOR gate 167 is turned into the “H” level, the refresh request is inputted to a refreshing pulse generator circuit 170, and a refresh enable signal RERF is outputted.
摘要翻译： 通过刷新定时器周期性地执行存储器单元的刷新，并避免存储器访问和存储器刷新之间的冲突。 当存储器访问发生时，通过来自OS电路161的单触发脉冲设置F / F 163，通过NOR门167将存储器访问请求输入到存储器访问脉冲发生器电路171，以及锁存控制信号LC和 输出使能信号REN。 当在存储器访问期间来自刷新定时器的刷新请求被输入到与门168时，或非门167的输出处于“L”电平，刷新请求由与门168阻止。此后， 当锁存控制信号LC变为“L”电平时，F / F 163,164和165被复位，或非门167的输出变成“H”电平，刷新请求被输入到 输出刷新脉冲发生器电路170和刷新使能信号RERF。
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公开(公告)号：US05999018A
公开(公告)日：1999-12-07
申请号：US986728
申请日：1997-12-08
申请人： Noriaki Komatsu
发明人： Noriaki Komatsu
IPC分类号： H03K19/173 , H03K19/0185
CPC分类号： H03K19/1736
摘要： A programmable buffer circuit includes a first stage circuit which receives an input signal IN indicative of a first or second value, and a second stage circuit, responsive to an output of the first stage circuit, for outputting one of a value designated depending on the value of the input signal and a value designated regardless of the value of the input signal. The second stage circuit includes a plurality of MOS transistors whose conduction properties change depending on whether ion implantation is applied thereto. By applying the ion implantation selectively to the MOS transistors, the second stage circuit is operated as a transfer logical function circuit or an inverter logical function circuit.
摘要翻译： 可编程缓冲电路包括接收表示第一或第二值的输入信号IN的第一级电路和响应于第一级电路的输出的第二级电路，用于输出根据值指定的值之一 的输入信号和与输入信号的值无关的值。 第二级电路包括多个MOS晶体管，其导电特性根据是否施加离子注入而改变。 通过将离子注入选择性地施加到MOS晶体管，第二级电路作为传输逻辑功能电路或逆变器逻辑功能电路工作。
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公开(公告)号：US07006401B2
公开(公告)日：2006-02-28
申请号：US10500400
申请日：2002-12-25
申请人： Hiroyuki Takahashi , Takuya Hirota , Noriaki Komatsu , Atsushi Nakagawa , Susumu Takano , Masahiro Yoshida , Yuuji Torige , Hideo Inaba
发明人： Hiroyuki Takahashi , Takuya Hirota , Noriaki Komatsu , Atsushi Nakagawa , Susumu Takano , Masahiro Yoshida , Yuuji Torige , Hideo Inaba
IPC分类号： G11C7/00
CPC分类号： G11C11/40603 , G11C11/406
摘要： Refresh of memory cells is performed periodically by a refresh timer, and collision between memory access and memory refresh is avoided. When memory access occurs, an F/F 163 is set by a one shot pulse from an OS circuit 161, a memory access request is inputted to a memory accessing pulse generator circuit 171 through a NOR gate 167, and a latch control signal LC and an enable signal REN are outputted. When a refresh request from the refresh timer is inputted to an AND gate 168 during the memory access, the output of the NOR gate 167 is at the “L” level, and the refresh request is blocked by the AND gate 168. Thereafter, at the time when the latch control signal LC is turned into the “L” level, F/Fs 163, 164 and 165 are reset, the output of the NOR gate 167 is turned into the “H” level, the refresh request is inputted to a refreshing pulse generator circuit 170, and a refresh enable signal RERF is outputted.
摘要翻译： 通过刷新定时器周期性地执行存储器单元的刷新，并避免存储器访问和存储器刷新之间的冲突。 当存储器访问发生时，通过来自OS电路161的单触发脉冲设置F / F 163，通过NOR门167将存储器访问请求输入到存储器访问脉冲发生器电路171，以及锁存控制信号LC和 输出使能信号REN。 当在存储器访问期间来自刷新定时器的刷新请求被输入到与门168时，或非门167的输出处于“L”电平，刷新请求由与门168阻止。 此后，当锁存控制信号LC变为“L”电平时，F / F 163,164和165被复位，或非门167的输出变为“H”电平，刷新请求 被输入到刷新脉冲发生器电路170，并且输出刷新使能信号RERF。
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公开(公告)号：US06944081B2
公开(公告)日：2005-09-13
申请号：US10363298
申请日：2001-08-30
申请人： Hiroyuki Takahashi , Atsushi Nakagawa , Yoshiyuki Katou , Hideo Inaba , Noriaki Komatsu , Takuya Hirota , Masahiro Yoshida
发明人： Hiroyuki Takahashi , Atsushi Nakagawa , Yoshiyuki Katou , Hideo Inaba , Noriaki Komatsu , Takuya Hirota , Masahiro Yoshida
IPC分类号： G11C11/406 , G11C7/00
CPC分类号： G11C11/406
摘要： A semiconductor memory device capable of a further reduction in power consumption for refresh operation is provided. Cell arrays S0, S1 are divided into respective four blocks B0˜B3 and B10˜B13. In a normal read/write operation, by address data designating a word line, one of the cell arrays is selected, and also one block is selected in the selected cell array, and further one word line is selected in the selected block. In a refresh operation, one of the cell arrays is selected, and four blocks in the selected cell array are simultaneously refreshed. Namely, respective one word line is selected from each of the four blocks, and the selected word lines are refreshed, thereby to reduce a power comsumption as compared to when the plural cell arrays are refreshed.
摘要翻译： 提供能够进一步降低刷新操作的功耗的半导体存储器件。 单元阵列S 0，S 1被分成四个块B 0〜B 3和B 10〜B 13。 在通常的读/写操作中，通过指定字线的地址数据，选择单元阵列中的一个，并且在所选择的单元阵列中选择一个块，并且在所选块中还选择一个字线。 在刷新操作中，选择单元阵列之一，同时刷新所选单元阵列中的四个块。 也就是说，从四个块中的每一个中选择相应的一个字线，并且与多个单元阵列刷新时相比，刷新所选择的字线，从而降低功耗。
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公开(公告)号：US06363027B1
公开(公告)日：2002-03-26
申请号：US09714301
申请日：2000-11-16
申请人： Noriaki Komatsu
发明人： Noriaki Komatsu
IPC分类号： G11C506
CPC分类号： G11C17/126
摘要： A semiconductor memory device comprises a plurality of first memory cells each located at an intersection of each of a plurality of word lines and an associated one of a plurality of bit lines and each having one end connected to the associated bit line; a plurality of memory cell blocks each comprising first memory cells; dummy cell blocks, provided among the memory cell blocks, for electrically isolating those memory cell blocks which are located at both ends from each other, each of the dummy cell blocks comprising second memory cells; main bit lines each provided for each of the memory cell blocks and each of the dummy cell blocks and each connected to an associated one of the bit lines; a main-bit-line control section for performing such control as to apply a predetermined voltage to the main bit lines, connect the main bit lines to associated sense amplifiers or set the main bit lines in an open state based on an address signal; virtual ground lines connected to other terminals of the first memory cells and the second memory cells; main virtual ground lines each provided for each of the memory cell blocks and each of the dummy cell blocks and each connected to an associated one of the virtual ground lines; and a main-virtual-ground-line control section for performing such control as to apply a predetermined voltage to the main virtual ground lines or set the main virtual ground lines in an open state based on an address signal.
摘要翻译： 半导体存储器件包括多个第一存储器单元，每个第一存储器单元各自位于多个字线中的每一个与多个位线中的相关联的一个的相交处，并且每个具有连接到相关联的位线的一端; 每个存储单元块包括第一存储器单元; 在存储单元块之间提供的用于将位于两端的那些存储单元块电隔离的虚拟单元块，每个虚设单元块包括第二存储单元; 每个存储器单元块和每个虚设单元块分别提供的主位线和每个连接到相关联的位线之一的位线; 主位线控制部分，用于执行对主位线施加预定电压的控制，将主位线连接到相关读出放大器或基于地址信号将主位线设置在打开状态; 连接到第一存储器单元和第二存储器单元的其它端子的虚拟接地线; 主虚拟接地线各自为每个存储单元块和虚拟单元块中的每一个提供，并且每个连接到虚拟接地线中的相关联的一个虚拟接地线; 以及主虚拟地线控制部分，用于执行对主虚拟接地线施加预定电压或基于地址信号将主虚拟接地线设置在打开状态的控制。
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公开(公告)号：US06084793A
公开(公告)日：2000-07-04
申请号：US984092
申请日：1997-12-03
申请人： Noriaki Komatsu
发明人： Noriaki Komatsu
CPC分类号： G11C17/12
摘要： A compact read-only memory (ROM) system with low current consumption and having a plurality of data lines and a word line, includes a first ROM cell having a gate connected to the word line and a source-drain path connected between a first data line and a second data line, a second ROM cell having a gate connected to the word line and a source-drain path connected between the second data line and a third data line, a third ROM cell having a gate connected to the word line and a source-drain path connected between the third data line and a fourth data line, and a sense amplifier for amplifying data from one of the ROM cells. The first data line is connected to a voltage source and the second data line is connected to the sense amplifier when data from the first ROM cell is read, and the third and fourth data lines are charged to a predetermined voltage.
摘要翻译： 具有低电流消耗且具有多条数据线和字线的紧凑型只读存储器（ROM）系统包括具有连接到字线的栅极的第一ROM单元和连接在第一数据之间的源极 - 漏极路径 线和第二数据线，具有连接到字线的栅极和连接在第二数据线和第三数据线之间的源极 - 漏极路径的第二ROM单元，具有连接到字线的栅极的第三ROM单元和 连接在第三数据线和第四数据线之间的源极 - 漏极路径，以及用于放大来自ROM单元之一的数据的读出放大器。 当读取来自第一ROM单元的数据，并且第三和第四数据线被充电到预定电压时，第一数据线连接到电压源，第二数据线连接到读出放大器。
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