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公开(公告)号：US06538653B1
公开(公告)日：2003-03-25
申请号：US08625241
申请日：1996-04-01
IPC分类号： G06T340
摘要： A graphic processing system has a processor for managing a display area and a character font area both included within an address space. From coded information indicative of a character transferred through a data bus of the system, the processor generates an address at which a character font pattern of the corresponding character has been stored and transfers that character font pattern to a predetermined position on the display area. The graphic processing system realizes high speed development of fonts.
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公开(公告)号：US5751930A
公开(公告)日：1998-05-12
申请号：US213820
申请日：1994-03-16
IPC分类号： G09G5/40 , G06F12/00 , G09G1/02 , G09G1/06 , G09G1/16 , G09G5/22 , G09G5/24 , G09G5/26 , G09G5/36 , G09G5/38 , G09G5/39 , G09G5/393 , G09G5/399 , G06T3/40 , G06T3/60
摘要： A graphic processing system for text display which includes a data processing unit, composed of a memory and a processing unit, for creating character code information, and a graphic data processing unit, composed of a graphic data processor and a frame buffer, for creating pixel information. The text display is performed by creating character code information in the data processing unit, supplying the character code information from the data processing unit to the graphic data processor, creating addresses on the frame buffer corresponding to the character code information by the graphic data processor, reading out a character font from a second area of the frame buffer using the created addresses, writing the read-out character font in a predetermined position of a first area of the frame buffer, and outputting the display data at the first area of the frame buffer to a display unit.
摘要翻译： 一种用于文本显示的图形处理系统，包括由用于创建字符代码信息的存储器和处理单元组成的数据处理单元，以及由图形数据处理器和帧缓冲器组成的用于创建像素的图形数据处理单元 信息。 通过在数据处理单元中产生字符代码信息，从数据处理单元向图形数据处理器提供字符代码信息，通过图形数据处理器创建对应于字符代码信息的帧缓冲器上的地址来执行文本显示， 使用所创建的地址从帧缓冲器的第二区域读出字符字体，将读出的字符字体写入帧缓冲器的第一区域的预定位置，并在帧的第一区域输出显示数据 缓冲到显示单元。
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公开(公告)号：US06697070B1
公开(公告)日：2004-02-24
申请号：US09454590
申请日：1999-12-07
IPC分类号： G06T1100
摘要： A graphic processing system has a processor for managing a display area and a character font area both include within an are disposed in the address space. From coded information indicative of a character transferred through a data bus of the system, the processor generates an address at which a character font pattern of the corresponding character has been stored and transfers that character font pattern to a predetermined position on the display area. The graphic processing system realizes high speed development of fonts.
摘要翻译： 图形处理系统具有用于管理显示区域的处理器和包括在地址空间内的字符字体区域。 从指示通过系统的数据总线传送的字符的编码信息中，处理器生成相应字符的字符字体图案已被存储的地址，并将该字符字体图案转移到显示区域上的预定位置。 图形处理系统实现了字体的高速发展。
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4.发明授权Graphic processing system for displaying characters and pictures at high speed 失效用于高速显示字符和图片的图形处理系统
公开(公告)号：US4947342A
公开(公告)日：1990-08-07
申请号：US905173
申请日：1986-09-09
IPC分类号： G09G5/40 , G06F12/00 , G09G1/02 , G09G1/06 , G09G1/16 , G09G5/22 , G09G5/24 , G09G5/26 , G09G5/36 , G09G5/38 , G09G5/39 , G09G5/393 , G09G5/399
摘要： A graphic processing system has a processor for managing a display area and a character font area both included within an address space. From coded information indicative of a character transferred through a data bus of the system, the processor generates an address at which a character font pattern of the corresponding character has been stored and transfers that character font pattern to a predetermined position on the display area. The graphic processing system realizes high speed development of fonts.
摘要翻译： 图形处理系统具有用于管理包括在地址空间内的显示区域和字符字体区域的处理器。 从指示通过系统的数据总线传送的字符的编码信息中，处理器生成相应字符的字符字体图案已被存储的地址，并将该字符字体图案转移到显示区域上的预定位置。 图形处理系统实现了字体的高速发展。
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5.发明授权Coprocessor executing pipeline control for executing protocols and instructions 失效协处理器执行流水线控制以执行协议和指令
公开(公告)号：US5504912A
公开(公告)日：1996-04-02
申请号：US830460
申请日：1992-02-05
申请人： Shigeki Morinaga , Norio Nakagawa , Mitsuru Watabe , Mamoru Ohba , Hiroyuki Kida , Hisashi Kaziwara , Takeshi Asai , Junichi Tatezaki
发明人： Shigeki Morinaga , Norio Nakagawa , Mitsuru Watabe , Mamoru Ohba , Hiroyuki Kida , Hisashi Kaziwara , Takeshi Asai , Junichi Tatezaki
IPC分类号： G06F7/00 , G06F9/38 , G06F15/16 , G06F15/167
CPC分类号： G06F9/3877 , G06F9/3885
摘要： The interface portion of a coprocessor is provided with a FIFO (First-In First-Out) buffer and means for accepting instructions in succession. Pipeline control of the instructions becomes possible in this way, and protocol means associated with a microprocessor is also provided.
摘要翻译： 协处理器的接口部分设置有FIFO（先进先出）缓冲器和用于连续接受指令的装置。 指令的流水线控制可以以这种方式进行，并且还提供了与微处理器相关联的协议装置。
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6.发明授权System for obtaining strict solution in accordance with accuracy of approximate solutions 失效根据近似解决方案的准确度获得严格解决方案的系统
公开(公告)号：US5631858A
公开(公告)日：1997-05-20
申请号：US89103
申请日：1993-08-12
申请人： Masahisa Narita , Hisashi Kaziwara , Takeshi Asai , Shigeki Morinaga , Hiroyuki Kida , Mitsuru Watabe , Tetsuaki Nakamikawa , Shunpei Kawasaki , Junichi Tatezaki , Norio Nakagawa , Yugo Kashiwagi
发明人： Masahisa Narita , Hisashi Kaziwara , Takeshi Asai , Shigeki Morinaga , Hiroyuki Kida , Mitsuru Watabe , Tetsuaki Nakamikawa , Shunpei Kawasaki , Junichi Tatezaki , Norio Nakagawa , Yugo Kashiwagi
CPC分类号： G06F7/57 , G06F7/535 , G06F7/5525 , G06F2207/3816 , G06F2207/5355 , G06F2207/5356 , G06F7/4873 , G06F7/49957
摘要： A multiplication, division and square root extraction apparatus which calculates the solutions to addition, division and square root extraction functions by approximation using iteration has a multiplier, an adder-subtracter and a shifter of prescribed bit width connected to a bus. Iteration is conducted by inputting the output of the multiplier to the adder-subtracter or the shifter and returning the result to the input of the multiplier via the bus. A shifter and an arithmetic and logic unit connected to a second bus connected to the aforesaid bus via a switch have a greater bit width than the prescribed bit width and are used for large scale calculations, thus preventing a reduction in processing speed.
摘要翻译： 通过使用迭代近似计算加法，除法和平方根提取函数的解的乘法，除法和平方根提取装置具有连接到总线的规定位宽的乘法器，加法器 - 减法器和移位器。 通过将乘法器的输出输入到加法器 - 减法器或移位器并通过总线将结果返回到乘法器的输入来进行迭代。 通过开关连接到连接到上述总线的第二总线的移位器和算术和逻辑单元具有比规定位宽更大的位宽度，并且用于大规模计算，从而防止处理速度的降低。
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公开(公告)号：US5293558A
公开(公告)日：1994-03-08
申请号：US536565
申请日：1990-07-03
申请人： Masahisa Narita , Hisashi Kaziwara , Takeshi Asai , Shigeki Morinaga , Hiroyuki Kida , Mitsuru Watabe , Tetsuaki Nakamikawa , Shunpei Kawasaki , Junichi Tatezaki , Norio Nakagawa , Yugo Kashiwagi
发明人： Masahisa Narita , Hisashi Kaziwara , Takeshi Asai , Shigeki Morinaga , Hiroyuki Kida , Mitsuru Watabe , Tetsuaki Nakamikawa , Shunpei Kawasaki , Junichi Tatezaki , Norio Nakagawa , Yugo Kashiwagi
CPC分类号： G06F7/57 , G06F7/535 , G06F7/5525 , G06F2207/3816 , G06F2207/5355 , G06F2207/5356 , G06F7/4873 , G06F7/49957
摘要： A multiplication, division and square root extraction apparatus which calculates the solutions to addition, division and square root extraction functions by approximation using iteration has a multiplier, an adder-subtracter and a shifter of prescribed bit width connected to a bus. Iteration is conducted by inputting the output of the multiplier to the adder-subtracter or the shifter and returning the result to the input of the multiplier via the bus. A shifter and an arithmetic and logic unit connected to a second bus connected to the aforesaid bus via a switch have a greater bit width than the prescribed bit width and are used for large scale calculations, thus preventing a reduction in processing speed.
摘要翻译： PCT No.PCT / JP89 / 01134 Sec。 371日期1990年7月3日 102（e）日期1990年7月3日PCT提交1989年11月2日PCT公布。 出版物WO90 / 05335 日期1990年5月17日。一种乘法，除法和平方根提取装置，其通过使用迭代近似来计算加法，除法和平方根提取函数的解，具有连接到a的规定位宽的乘法器，加法器 - 减法器和移位器 总线。 通过将乘法器的输出输入到加法器 - 减法器或移位器并通过总线将结果返回到乘法器的输入来进行迭代。 通过开关连接到连接到上述总线的第二总线的移位器和算术和逻辑单元具有比规定位宽更大的位宽度，并且用于大规模计算，从而防止处理速度的降低。
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8.发明授权System using microprocessor address lines for coprocessor selection within a multi-coprocessor apparatus 失效在多协处理器装置中使用微处理器地址线进行协处理器选择的系统
公开(公告)号：US5125095A
公开(公告)日：1992-06-23
申请号：US678906
申请日：1991-03-28
申请人： Takuichiro Nakazawa , Makoto Hanawa , Atsushi Hasegawa , Ikuya Kawasaki , Kazuhiko Iwasaki , Shigeki Morinaga , Hisashi Kaziwara , Takeshi Asai , Junichi Tatezaki
发明人： Takuichiro Nakazawa , Makoto Hanawa , Atsushi Hasegawa , Ikuya Kawasaki , Kazuhiko Iwasaki , Shigeki Morinaga , Hisashi Kaziwara , Takeshi Asai , Junichi Tatezaki
IPC分类号： G06F9/38 , G06F15/16 , G06F15/177
CPC分类号： G06F9/3877 , G06F9/3885
摘要： A microcomputer system has a microprocessor and a number of independent coprocessors for executing individual instructions according to instruction data sent from the microprocessor. An address bus and a data bus interconnect the coprocessors with the microprocessor. The microprocessor sends instruction data to the coprocessors via the data bus and concurrently sends coprocessor designation data to the coprocessors via the address bus. The coprocessor designated by the designation data reads and reacts to the instruction data while the other coprocessors within the system disregard the instruction data.
摘要翻译： 微计算机系统具有微处理器和多个独立的协处理器，用于根据从微处理器发送的指令数据执行各个指令。 地址总线和数据总线将协处理器与微处理器互连。 微处理器通过数据总线向协处理器发送指令数据，同时通过地址总线向协处理器发送协处理器指定数据。 由指定数据指定的协处理器读取并对指令数据进行响应，而系统内的其他协处理器忽略指令数据。
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公开(公告)号：US5956263A
公开(公告)日：1999-09-21
申请号：US797653
申请日：1997-01-31
申请人： Masahisa Narita , Hisashi Kaziwara , Takeshi Asai , Shigeki Morinaga , Hiroyuki Kida , Mitsuru Watabe , Tetsuaki Nakamikawa , Shunpei Kawasaki , Junichi Tatezaki , Norio Nakagawa , Yugo Kashiwagi
发明人： Masahisa Narita , Hisashi Kaziwara , Takeshi Asai , Shigeki Morinaga , Hiroyuki Kida , Mitsuru Watabe , Tetsuaki Nakamikawa , Shunpei Kawasaki , Junichi Tatezaki , Norio Nakagawa , Yugo Kashiwagi
CPC分类号： G06F7/57 , G06F7/535 , G06F7/5525 , G06F2207/3816 , G06F2207/5355 , G06F2207/5356 , G06F7/4873 , G06F7/49957
摘要： A multiplication, division and square root extraction apparatus which calculates the solutions to addition, division and square root extraction functions by approximation using iteration has a multiplier, an adder-subtracter and a shifter of prescribed bit width connected to a bus. Iteration is conducted by inputting the output of the multiplier to the adder-subtracter or the shifter and returning the result to the input of the multiplier via the bus. A shifter and an arithmetic and logic unit connected to a second bus connected to the aforesaid bus via a switch have a greater bit width than the prescribed bit width and are used for large scale calculations, thus preventing a reduction in processing speed.
摘要翻译： 通过使用迭代近似计算加法，除法和平方根提取函数的解的乘法，除法和平方根提取装置具有连接到总线的规定位宽的乘法器，加法器 - 减法器和移位器。 通过将乘法器的输出输入到加法器 - 减法器或移位器并通过总线将结果返回到乘法器的输入来进行迭代。 通过开关连接到连接到上述总线的第二总线的移位器和算术和逻辑单元具有比规定位宽更大的位宽度，并且用于大规模计算，从而防止处理速度的降低。
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