-
公开(公告)号：US5751930A
公开(公告)日：1998-05-12
申请号：US213820
申请日：1994-03-16
IPC分类号： G09G5/40 , G06F12/00 , G09G1/02 , G09G1/06 , G09G1/16 , G09G5/22 , G09G5/24 , G09G5/26 , G09G5/36 , G09G5/38 , G09G5/39 , G09G5/393 , G09G5/399 , G06T3/40 , G06T3/60
摘要： A graphic processing system for text display which includes a data processing unit, composed of a memory and a processing unit, for creating character code information, and a graphic data processing unit, composed of a graphic data processor and a frame buffer, for creating pixel information. The text display is performed by creating character code information in the data processing unit, supplying the character code information from the data processing unit to the graphic data processor, creating addresses on the frame buffer corresponding to the character code information by the graphic data processor, reading out a character font from a second area of the frame buffer using the created addresses, writing the read-out character font in a predetermined position of a first area of the frame buffer, and outputting the display data at the first area of the frame buffer to a display unit.
摘要翻译： 一种用于文本显示的图形处理系统，包括由用于创建字符代码信息的存储器和处理单元组成的数据处理单元，以及由图形数据处理器和帧缓冲器组成的用于创建像素的图形数据处理单元 信息。 通过在数据处理单元中产生字符代码信息，从数据处理单元向图形数据处理器提供字符代码信息，通过图形数据处理器创建对应于字符代码信息的帧缓冲器上的地址来执行文本显示， 使用所创建的地址从帧缓冲器的第二区域读出字符字体，将读出的字符字体写入帧缓冲器的第一区域的预定位置，并在帧的第一区域输出显示数据 缓冲到显示单元。
-
公开(公告)号：US06538653B1
公开(公告)日：2003-03-25
申请号：US08625241
申请日：1996-04-01
IPC分类号： G06T340
摘要： A graphic processing system has a processor for managing a display area and a character font area both included within an address space. From coded information indicative of a character transferred through a data bus of the system, the processor generates an address at which a character font pattern of the corresponding character has been stored and transfers that character font pattern to a predetermined position on the display area. The graphic processing system realizes high speed development of fonts.
-
公开(公告)号：US06697070B1
公开(公告)日：2004-02-24
申请号：US09454590
申请日：1999-12-07
IPC分类号： G06T1100
摘要： A graphic processing system has a processor for managing a display area and a character font area both include within an are disposed in the address space. From coded information indicative of a character transferred through a data bus of the system, the processor generates an address at which a character font pattern of the corresponding character has been stored and transfers that character font pattern to a predetermined position on the display area. The graphic processing system realizes high speed development of fonts.
摘要翻译： 图形处理系统具有用于管理显示区域的处理器和包括在地址空间内的字符字体区域。 从指示通过系统的数据总线传送的字符的编码信息中，处理器生成相应字符的字符字体图案已被存储的地址，并将该字符字体图案转移到显示区域上的预定位置。 图形处理系统实现了字体的高速发展。
-
4.发明授权Graphic processing system for displaying characters and pictures at high speed 失效用于高速显示字符和图片的图形处理系统
公开(公告)号：US4947342A
公开(公告)日：1990-08-07
申请号：US905173
申请日：1986-09-09
IPC分类号： G09G5/40 , G06F12/00 , G09G1/02 , G09G1/06 , G09G1/16 , G09G5/22 , G09G5/24 , G09G5/26 , G09G5/36 , G09G5/38 , G09G5/39 , G09G5/393 , G09G5/399
摘要： A graphic processing system has a processor for managing a display area and a character font area both included within an address space. From coded information indicative of a character transferred through a data bus of the system, the processor generates an address at which a character font pattern of the corresponding character has been stored and transfers that character font pattern to a predetermined position on the display area. The graphic processing system realizes high speed development of fonts.
摘要翻译： 图形处理系统具有用于管理包括在地址空间内的显示区域和字符字体区域的处理器。 从指示通过系统的数据总线传送的字符的编码信息中，处理器生成相应字符的字符字体图案已被存储的地址，并将该字符字体图案转移到显示区域上的预定位置。 图形处理系统实现了字体的高速发展。
-
公开(公告)号：US4720708A
公开(公告)日：1988-01-19
申请号：US686594
申请日：1984-12-26
申请人： Hiroshi Takeda , Shigeaki Yoshida , Koyo Katsura
发明人： Hiroshi Takeda , Shigeaki Yoshida , Koyo Katsura
CPC分类号： G09G5/12
摘要： A CRT (cathode ray tube) controller for controlling one CRT device in an interlace mode has a synchronizing circuit of bi-directional construction, in order to make possible synchronous operation of the CRT controller with other circuits (other CRT controllers or a TV system). When the CRTC is used as a master circuit of a CRT display system, a synchronizing signal is derived from the synchronizing circuit in synchronization with a count signal of a vertical scanning counter and an output of an interlace controller of the CRTC, and is supplied to a synchronizing terminal of the other CRTCs. Scanning counters and a flip-flop for controlling an interlace operation of the other CRTCs are reset to their initial state in synchronization with the synchronizing signal. When the CRTC is used as a slave circuit, scanning counters and a flip-flop of the CRTC are reset to their initial state in synchronization with the external synchronizing signal.
摘要翻译： 用于以隔行模式控制一个CRT器件的CRT（阴极射线管）控制器具有双向结构的同步电路，以便使CRT控制器与其他电路（其它CRT控制器或TV系统）可以同步操作， 。 当CRTC用作CRT显示系统的主电路时，与垂直扫描计数器的计数信号和CRTC的隔行控制器的输出同步地从同步电路导出同步信号，并将其提供给 其他CRTC的同步终端。 用于控制其它CRTC的隔行扫描的扫描计数器和触发器与同步信号同步地被复位到其初始状态。 当CRTC用作从电路时，与外部同步信号同步，将扫描计数器和CRTC的触发器复位到初始状态。
-
公开(公告)号：US5610622A
公开(公告)日：1997-03-11
申请号：US309413
申请日：1994-09-20
申请人： Hiroshi Takeda , Shigeaki Yoshida , Koyo Katsura
发明人： Hiroshi Takeda , Shigeaki Yoshida , Koyo Katsura
CPC分类号： G09G5/12
摘要： A CRT (cathode ray tube) controller for controlling one CRT device in an interlace mode has a synchronizing circuit of bi-directional construction, in order to make possible synchronous operation of the CRT controller with other circuits (other CRT controllers or a TV system). When the CRTC is used as a master circuit of a CRT display system, a synchronizing signal is derived from the synchronizing circuit in synchronization on with a count signal of a vertical scanning counter and an output of an interlace controller of the CRTC, and is supplied to a synchronizing terminal of the other CRTCs. Scanning counters and a flip-flop for controlling an interlace operation of the other CRTCs are reset to their initial state in synchronization with the synchronizing signal. When the CRTC is used as a slave circuit, scanning counters and a flip-flop of the CRTC are reset to their initial state in synchronization with the external synchronizing signal.
摘要翻译： 用于以隔行模式控制一个CRT器件的CRT（阴极射线管）控制器具有双向结构的同步电路，以便使CRT控制器与其他电路（其它CRT控制器或TV系统）可以同步操作， 。 当CRTC用作CRT显示系统的主电路时，根据垂直扫描计数器的计数信号和CRTC的隔行控制器的输出，同步信号从同步电路得到，并被提供 到其他CRTC的同步终端。 用于控制其他CRTC的隔行扫描的扫描计数器和触发器与同步信号同步地被复位到其初始状态。 当CRTC用作从电路时，与外部同步信号同步，将扫描计数器和CRTC的触发器复位到初始状态。
-
公开(公告)号：US4904990A
公开(公告)日：1990-02-27
申请号：US144279
申请日：1988-01-15
申请人： Hiroshi Takeda , Shigeaki Yoshida , Koyo Katsura
发明人： Hiroshi Takeda , Shigeaki Yoshida , Koyo Katsura
CPC分类号： G09G5/12
摘要： A CRT (cathode ray tube) controller for controlling one CRT device in an interlace mode has a synchronizing circuit of bi-directional construction, in order to make possible synchronous operation of the CRT controller with other circuits (other CRT controllers or a TV system). When the CRTC is used as a master circuit of a CRT display system, a synchronizing signal is derived from the synchronizing circuit in synchronization with a count signal of a vertical scanning counter and an output of an interlace controller of the CRTC, and is supplied to a synchronizing terminal of the other CRTCs. Scanning counters and a flip-flop for controlling an interlace operation of the other CRTCs are reset to their initial state in synchronization with the synchronizing signal. When the CRTC is used as a slave circuit, scanning counters and a flip-flop of the CRTC are reset to their initial state in synchronization with the external synchronizing signal.
-
公开(公告)号：US5606338A
公开(公告)日：1997-02-25
申请号：US309411
申请日：1994-09-20
申请人： Hiroshi Takeda , Shigeaki Yoshida , Koyo Katsura
发明人： Hiroshi Takeda , Shigeaki Yoshida , Koyo Katsura
CPC分类号： G09G5/12
摘要： A CRT (cathode ray tube) controller for controlling one CRT device in an interlace mode has a synchronizing circuit of bi-directional construction, in order to make possible synchronous operation of the CRT controller with other circuits (other CRT controllers or a TV system). When the CRTC is used as a master circuit of a CRT display system, a synchronizing signal is derived from the synchronizing circuit in synchronization with a count signal of a vertical scanning counter and an output of an interlace controller of the CRTC, and is supplied to a synchronizing terminal of the other CRTCs. Scanning counters and a flip-flop for controlling an interlace operation of the other CRTCs are reset to their initial state in synchronization with the synchronizing signal. When the CRTC is used as a slave circuit, scanning counters and a flip-flop of the CRTC are reset to their initial state in synchronization with the external synchronizing signal.
摘要翻译： 用于以隔行模式控制一个CRT器件的CRT（阴极射线管）控制器具有双向结构的同步电路，以便使CRT控制器与其他电路（其它CRT控制器或TV系统）可以同步操作， 。 当CRTC用作CRT显示系统的主电路时，与垂直扫描计数器的计数信号和CRTC的隔行控制器的输出同步地从同步电路导出同步信号，并将其提供给 其他CRTC的同步终端。 用于控制其他CRTC的隔行扫描的扫描计数器和触发器与同步信号同步地被复位到其初始状态。 当CRTC用作从电路时，与外部同步信号同步，将扫描计数器和CRTC的触发器复位到初始状态。
-
公开(公告)号：US4757310A
公开(公告)日：1988-07-12
申请号：US626992
申请日：1984-07-02
申请人： Koyo Katsura , Hideo Maejima , Hiroshi Takeda
发明人： Koyo Katsura , Hideo Maejima , Hiroshi Takeda
IPC分类号： G06F3/153 , G06F3/14 , G09G1/02 , G09G5/14 , G09G5/32 , G09G5/36 , G09G5/377 , G09G5/39 , G09G5/395 , G09G5/397 , G09G1/16
摘要： In an image displaying field where there is a tendency which will increase the data to be handled in accordance with the high integration of a display device, a CRT controller according to the present invention improves the superposed display and the responsiveness of the display and drawing operations by dividing a unit clock into a predetermined number to function with high speed and a multifunction display. When image data are to be inputted to or outputted from a refresh memory corresponding to a display frame, the memory content and the display address are assigned at a ratio of 1:n to effect the processings in parallel. As a result, the time period utilized by the display cycle of the prior art can be assigned to the drawing operation so that the processing can be speeded up while making it easier than the prior art to effect the superposed display of letters, symbols and drawings. The resultant effect is that it is unnecessary to increase the number of refresh memories corresponding to the displayed frame and that the external parts can be simplified to contribute to the improvement in the reliability.
摘要翻译： 在根据显示装置的高集成度存在将增加要处理的数据的趋势的图像显示领域中，根据本发明的CRT控制器改进了叠加显示和显示和绘图操作的响应性 通过将单位时钟分割成预定数量以高速功能和多功能显示。 当图像数据要被输入到与显示帧相对应的刷新存储器中时，以1：n的比例分配存储器内容和显示地址以并行地进行处理。 结果，可以将现有技术的显示循环所使用的时间段分配给绘制操作，使得可以加速处理，同时使现有技术更容易实现字母，符号和图纸的叠加显示 。 所产生的效果是不需要增加对应于所显示的帧的刷新存储器的数量，并且可以简化外部部件以有助于提高可靠性。
-
公开(公告)号：US5696540A
公开(公告)日：1997-12-09
申请号：US799889
申请日：1991-12-02
申请人： Koyo Katsura , Hideo Maejima , Hiroshi Takeda
发明人： Koyo Katsura , Hideo Maejima , Hiroshi Takeda
IPC分类号： G06F3/153 , G06F3/14 , G09G1/02 , G09G5/14 , G09G5/32 , G09G5/36 , G09G5/377 , G09G5/39 , G09G5/395 , G09G5/397 , G09G1/00
摘要： In an image displaying field where there is a tendency which will increase the data to be handled in accordance with the high integration of a display device, a CRT controller according to the present invention improves the superposed display and the responsiveness of the display and drawing operations by dividing a unit clock into a predetermined number to function with high speed and a multifunction display. When image data are to be inputted to or outputted from a refresh memory corresponding to a display frame, the memory content and the display address are assigned at a ratio of 1:n to effect the processings in parallel. As a result, the time period utilized by the display cycle of the prior art can be assigned to the drawing operation so that the processing can be speeded up while making it easier than the prior art to effect the superposed display of letters, symbols and drawings. The resultant effect is that it is unnecessary to increase the number of refresh memories corresponding to the displayed frame and that the external parts can be simplified to contribute to the improvement in the reliability.
摘要翻译： 在根据显示装置的高集成度存在将增加要处理的数据的趋势的图像显示领域中，根据本发明的CRT控制器改进了叠加显示和显示和绘图操作的响应性 通过将单位时钟分割成预定数量以高速功能和多功能显示。 当图像数据要被输入到与显示帧相对应的刷新存储器中时，以1：n的比例分配存储器内容和显示地址以并行地进行处理。 结果，可以将现有技术的显示循环所使用的时间段分配给绘制操作，使得可以加速处理，同时使现有技术更容易实现字母，符号和图纸的叠加显示 。 所产生的效果是不需要增加对应于所显示的帧的刷新存储器的数量，并且可以简化外部部件以有助于提高可靠性。
-
-
-
-
-
-
-
-
-
搜索结果
134 条记录 (耗时 0.041 秒)