-
1.发明授权Integrated circuit with error correction mechanisms to offset narrow tolerancing 有权具有纠错机制的集成电路，以抵消窄公差公开(公告)号：US07701240B2
公开(公告)日：2010-04-20
申请号：US11301240
申请日：2005-12-13
申请人： Krisztian Flautner , David Michael Bull , Todd Michael Austin , David Theodore Blaauw , Trevor Nigel Mudge
发明人： Krisztian Flautner , David Michael Bull , Todd Michael Austin , David Theodore Blaauw , Trevor Nigel Mudge
CPC分类号： G06F11/24
摘要： An integrated circuit 2 has a specified range of runtime-variable operating parameters. Data processing circuits 4 within the integrated circuit 2 have associated error detection and error repair mechanisms 6. When operating within a narrow typical-case range of runtime-variable operating parameters the data processing circuits 4 operate correctly and substantially without error. When operating outside of this typical-case range but inside the specified range of permitted values for the run-time variable operating parameters, then the error detection and error repair circuit 6 operate to repair the errors which occur.
摘要翻译： 集成电路2具有指定范围的运行时变量运行参数。 集成电路2内的数据处理电路4具有相关联的错误检测和错误修复机制6.当在运行时间可变的运行参数的窄典型情况范围内操作时，数据处理电路4正确且基本上没有错误地操作。 当在这种典型情况范围之外运行，但在运行时变量运行参数的允许值的指定范围内时，错误检测和错误修复电路6操作以修复发生的错误。
-
公开(公告)号：US08185812B2
公开(公告)日：2012-05-22
申请号：US11636716
申请日：2006-12-11
IPC分类号： G06F11/00
CPC分类号： G06F11/1695 , G06F11/0721 , G06F11/0793 , G06F11/104 , G06F11/1608 , G06F11/167 , G06F11/183
摘要： An integrated circuit 2 includes logic circuitry 10 and sequential storage elements 8. Both the logic circuit 10 and sequential storage elements 8 can be subject to particle strikes giving rise to single event upset errors. These single event upset errors can be detected by detecting a transition in the stored value stored by the sequential storage elements 8 occurring outside of a valid transition period associated with that sequential storage element 8.
摘要翻译： 集成电路2包括逻辑电路10和顺序存储元件8.逻辑电路10和顺序存储元件8都可能经受粒子撞击，从而引起单事件失真错误。 可以通过检测在与该顺序存储元件8相关联的有效过渡时段之外发生的顺序存储元件8存储的存储值中的转变来检测这些单事件中断错误。
-
公开(公告)号：US08103922B2
公开(公告)日：2012-01-24
申请号：US13162308
申请日：2011-06-16
IPC分类号： G11C29/00
CPC分类号： G01R31/3177
摘要： An integrated circuit is provided with domino logic including a speculative node and a checker node. Precharged circuitry precharges both the speculative node and the checker node. Logic circuitry provides a discharge path for the speculative node and the checker node in dependence upon input signal values. Evaluation control circuitry first couples the speculative node to the logic circuitry and then subsequently couples the checker node to the logic circuitry such that these can be discharged if the input signals to the logic circuitry have appropriate values. Error detection circuitry detects an error when the speculative node and the checker node are not one of both discharged or both undischarged.
摘要翻译： 集成电路提供有多米诺逻辑，包括推测节点和检查器节点。 预充电电路对推测节点和检查器节点进行预充电。 逻辑电路根据输入信号值为推测节点和校验器节点提供放电路径。 评估控制电路首先将推测节点耦合到逻辑电路，然后随后将校验器节点耦合到逻辑电路，使得如果逻辑电路的输入信号具有适当的值，则它们可以被放电。 当推测节点和检查器节点都不是放电或未放电的两者之一时，错误检测电路检测到错误。
-
公开(公告)号：US08006147B2
公开(公告)日：2011-08-23
申请号：US12382427
申请日：2009-03-16
IPC分类号： G11C29/00
CPC分类号： G01R31/3177
摘要： An integrated circuit is provided with domino logic including a speculative node and a checker node. Precharged circuitry precharges both the speculative node and the checker node. Logic circuitry provides a discharge path for the speculative node and the checker node in dependence upon input signal values. Evaluation control circuitry first couples the speculative node to the logic circuitry and then subsequently couples the checker node to the logic circuitry such that these can be discharged if the input signals to the logic circuitry have appropriate values. Error detection circuitry detects an error when the speculative node and the checker node are not one of both discharged or both undischarged.
摘要翻译： 集成电路提供有多米诺逻辑，包括推测节点和检查器节点。 预充电电路对推测节点和检查器节点进行预充电。 逻辑电路根据输入信号值为推测节点和校验器节点提供放电路径。 评估控制电路首先将推测节点耦合到逻辑电路，然后随后将校验器节点耦合到逻辑电路，使得如果逻辑电路的输入信号具有适当的值，则它们可以被放电。 当推测节点和检查器节点都不是放电或未放电的两者之一时，错误检测电路检测到错误。
-
公开(公告)号：US20100235697A1
公开(公告)日：2010-09-16
申请号：US12382427
申请日：2009-03-16
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/3177
摘要： An integrated circuit 2 is provided with domino logic including a speculative node 22 and a checker node 24. Precharged circuitry 36 precharges both the speculative node and the checker node. Logic circuitry 26 provides a discharge path for the speculative node and the checker node in dependence upon input signal values. Evaluation control circuitry 28, 30 first couples the speculative node to the logic circuitry and then subsequently couples the checker node to the logic circuitry such that these can be discharged if the input signals to the logic circuitry 26 have appropriate values. Error detection circuitry 32 detects an error when the speculative node and the checker node are not one of both discharged or both undischarged.
摘要翻译： 集成电路2具有包括推测节点22和检验器节点24的多米诺逻辑逻辑。预充电电路36对推测节点和检验器节点进行预充电。 逻辑电路26根据输入信号值提供推测节点和校验器节点的放电路径。 评估控制电路28,30首先将推测节点耦合到逻辑电路，然后随后将校验器节点耦合到逻辑电路，使得如果逻辑电路26的输入信号具有适当的值，则它们可以被放电。 错误检测电路32在推测节点和检查器节点都不是放电的两者之一或两者未被充电时检测错误。
-
公开(公告)号：US07263015B2
公开(公告)日：2007-08-28
申请号：US11267574
申请日：2005-11-07
CPC分类号： G11C11/418 , G11C8/08 , G11C8/10
摘要： A signal capture element for providing a first pre-charged logic level as first and second interim address portion signals during a pre-charged period and outputting during an evaluate period an address portion logic level as the first interim address portion signal and an inverted address portion logic level as the second interim address portion signal. First and second address portion signals are derivable respectively from first and second interim address portion signals. An inverter circuit for outputting to an address decoder during a pre-charged period a second pre-charged logic level as the first and second address portion signals. The inverter circuit having transfer characteristics that maintain voltage levels such that the first and second address portion signals are interpreted to be at the second pre-charged logic level despite the first or second interim address portion signal failing to transition to a valid logic level during the evaluate period.
摘要翻译： 一种信号捕捉元件，用于在预充电周期期间提供第一预充电逻辑电平作为第一和第二中间地址部分信号，并且在评估周期期间输出地址部分逻辑电平作为第一中间地址部分信号和反相地址部分 逻辑电平作为第二临时地址部分信号。 第一和第二地址部分信号可以分别从第一和第二临时地址部分信号导出。 一种逆变器电路，用于在预充电周期期间将作为第一和第二地址部分信号的第二预充电逻辑电平输出到地址译码器。 逆变器电路具有保持电压电平的传输特性，使得第一和第二地址部分信号被解释为处于第二预充电逻辑电平，尽管第一或第二临时地址部分信号在期间不能转换到有效逻辑电平 评估期
-
7.发明授权Error recovery following speculative execution with an instruction processing pipeline 有权使用指令处理流水线进行推测执行后出错恢复公开(公告)号：US09519538B2
公开(公告)日：2016-12-13
申请号：US13067510
申请日：2011-06-06
申请人： Emre Özer , Shidhartha Das , David Michael Bull
发明人： Emre Özer , Shidhartha Das , David Michael Bull
CPC分类号： G06F11/0793 , G06F9/3842 , G06F9/3851 , G06F9/3863 , G06F9/3867 , G06F11/0721
摘要： An instruction processing pipeline having error detection and error recovery circuitry associated with one or more of the pipeline stages. If an error is detected within a signal value within that pipeline stage, then it can be repaired. Part of the error recovery may be to flush upstream program instructions from the instruction pipeline. When multi-threading, only those instructions from a thread including an instruction which has been lost as a consequence of the error recovery need be flushed from the instruction pipeline. The instruction pipeline may additionally/alternatively be provided with more than one main storage element associated with each signal value with these main storage elements used in an alternating fashion such that if a signal value has been erroneously captured and needs to be repaired, there is still available a main storage element to properly capture the signal value corresponding to the following program instruction.
摘要翻译： 具有与一个或多个流水线级相关联的错误检测和错误恢复电路的指令处理流水线。 如果在该流水线阶段内的信号值内检测到错误，则可以进行修复。 部分错误恢复可能是从指令流水线中刷新上游程序指令。 当多线程时，只有来自包括作为错误恢复的结果已经丢失的指令的线程的那些指令需要从指令流水线中刷新。 指令流水线可以另外/替代地设置有与每个信号值相关联的多于一个主存储元件，这些主存储元件以交替方式使用，使得如果信号值被错误地捕获并且需要被修复，则仍然存在 可用主存储元件来适当地捕获与以下程序指令对应的信号值。
-
公开(公告)号：US08640008B2
公开(公告)日：2014-01-28
申请号：US13336428
申请日：2011-12-23
IPC分类号： H03M13/00
CPC分类号： G06F11/1407 , G06F11/1497
摘要： A data processing apparatus has error detection units each configured to generate an error signal if a first and second sample of a signal associated with execution of an instruction differ. Error value generation circuitry generates an error value showing if any of the error detection units have generated the error signal. Error value stabilisation circuitry performs a stabilisation procedure comprising re-sampling the error value to remove metastability. Error recovery circuitry initiates re-execution of the instruction if the error value is asserted. Count circuitry holds a counter value in association with the error value, the counter value set to a predetermined value when the error value is generated and decremented each time the error value is re-sampled prior to reaching the error value stabilisation circuitry. The error value bypasses the stabilisation procedure if the counter value is zero before the error value reaches the error value stabilisation circuitry.
摘要翻译： 数据处理装置具有错误检测单元，每个错误检测单元被配置为如果与指令的执行相关联的信号的第一和第二采样不同，则生成错误信号。 错误值产生电路产生一个错误值，显示任何错误检测单元是否产生了错误信号。 误差值稳定电路执行稳定程序，包括重新采样误差值以消除亚稳态。 错误恢复电路如果错误值被确认则启动指令的重新执行。 计数电路与错误值相关联地保持计数器值，当误差值被产生并且每当在到达误差值稳定电路之前重新采样误差值时递减，计数器值被设置为预定值。 如果在错误值到达故障值稳定电路之前计数器值为零，则误差值会绕过稳定程序。
-
公开(公告)号：US08621272B2
公开(公告)日：2013-12-31
申请号：US12735339
申请日：2008-12-29
申请人： Shidhartha Das , David Michael Bull , Emre Ozer
发明人： Shidhartha Das , David Michael Bull , Emre Ozer
IPC分类号： G06F11/00
CPC分类号： G06F11/0793 , G01R31/31816 , G06F11/1076 , G06F11/1608
摘要： An integrated circuit is provided with error detection circuitry and error repair circuitry. Error tolerance circuitry is responsive to a control parameter to selectively disable the error repair circuitry. The control parameter is dependent on the processing performed within the circuit. For example, the control parameter may be generated in dependence upon the program instruction being executed, the output signal value which is in error, the previous behavior of the circuit or in other ways.
-
10.发明申请Error recovery following speculative execution with an instruction processing pipeline 有权使用指令处理流水线进行推测执行后出错恢复公开(公告)号：US20120131313A1
公开(公告)日：2012-05-24
申请号：US13067510
申请日：2011-06-06
申请人： Emre Ozer , Shidhartha Das , David Michael Bull
发明人： Emre Ozer , Shidhartha Das , David Michael Bull
CPC分类号： G06F11/0793 , G06F9/3842 , G06F9/3851 , G06F9/3863 , G06F9/3867 , G06F11/0721
摘要： An instruction processing pipeline 6 is provided. This has error detection and error recovery circuitry 20 associated with one or more of the pipeline stages. If an error is detected within a signal value within that pipeline stage, then it can be repaired. Part of the error recovery may be to flush upstream program instructions from the instruction pipeline 6. When multi-threading, only those instructions from a thread including an instruction which has been lost as a consequence of the error recovery need to be flushed from the instruction pipeline 6. Instruction can also be selected for flushing in dependence upon characteristics such as privileged level, number of dependent instructions etc. The instruction pipeline may additionally/alternatively be provided with more than one main storage element 26, 28 associated with each signal value with these main storage elements 26, 28 being used in an alternating fashion such that if a signal value has been erroneously captured and needs to be repaired, there is still available a main storage element 26, 28 to properly capture the signal value corresponding to the following program instruction. In this way flushes can be avoided.
摘要翻译： 提供了指令处理流水线6。 这具有与一个或多个流水线级相关联的错误检测和错误恢复电路20。 如果在该流水线阶段内的信号值内检测到错误，则可以进行修复。 错误恢复的一部分可能是从指令流水线6冲洗上游程序指令。当多线程时，只有来自包括作为错误恢复的结果已经丢失的指令的线程的那些指令需要从指令中刷新 流水线6.也可以根据诸如特权级别，依赖指令数量等特征来选择刷新指令。指令流水线可以另外地或替代地设置有多个主存储元件26,28，其与每个信号值相关联， 这些主存储元件26,28以交替的方式使用，使得如果信号值被错误地捕获并且需要修复，则仍然可以使用主存储元件26,28来适当地捕获对应于以下的信号值 程序指令。 这样可以避免冲洗。
-
-
-
-
-
-
-
-
-
搜索结果
64 条记录 (耗时 0.026 秒)
