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    Multi-processor system
    1.
    发明授权
    Multi-processor system 有权
    多处理器系统

    公开(公告)号：US07836233B2

    公开(公告)日：2010-11-16

    申请号：US10642755

    申请日：2003-08-19

    申请人： Kunihiko Tsunedomi ,  Kentaro Yoshimura ,  Nobuyasu Kanekawa ,  Takanori Yokoyama ,  Mitsuru Watabe

    发明人： Kunihiko Tsunedomi ,  Kentaro Yoshimura ,  Nobuyasu Kanekawa ,  Takanori Yokoyama ,  Mitsuru Watabe

    IPC分类号： G06F13/00

    CPC分类号： G05B19/0421 ,  G05B2219/2231 ,  G05B2219/25178

    摘要： A serial communication interface (SCI) cable 4 is provided between the slave processor 2 and the master processor 3. Both processors are connected with a communication interface for peripheral units (SPI: Serial Peripheral Interface) which enables fast transmission. The slave processor 2 transmits a transmission request command which requests at least one of data transmission and reception from the command communication section 220 to the master processor 3 through the SCI cable 4. The master processor 3 transfers data to and from the slave processor 2 in communication with the slave processor 2 by means of the data communication section 310 through the fast SPI cable 5 in response to a transmission request command sent from the slave processor 2 With this, the processing ability of a multi-processor system can be increased.

    摘要翻译： 在从属处理器2和主处理器3之间提供串行通信接口（SCI）电缆4.两个处理器都连接有外围设备的通信接口（SPI：串行外设接口），可实现快速传输。 从处理器2通过SCI电缆4发送从命令通信部220向主处理器3请求数据发送和接收中的至少一个的发送请求命令。主处理器3将来自从处理器2的数据传送到从处理器2 响应于从从属处理器2发送的发送请求命令，通过数据通信部分310通过快速SPI电缆5与从属处理器2进行通信。由此，可以增加多处理器系统的处理能力。

    Data communication system with an SPI bus having a plurality of devices wherein data communications are enabled using communication protocols optimum to respective devices
    4.
    发明授权
    Data communication system with an SPI bus having a plurality of devices wherein data communications are enabled using communication protocols optimum to respective devices 有权
    具有SPI总线的数据通信系统具有多个设备，其中使用对各个设备最佳的通信协议来启用数据通信

    公开(公告)号：US07228372B2

    公开(公告)日：2007-06-05

    申请号：US11016769

    申请日：2004-12-21

    申请人： Kentaro Yoshimura ,  Wataru Nagaura ,  Takanori Yokoyama ,  Nobuyasu Kanekawa

    发明人： Kentaro Yoshimura ,  Wataru Nagaura ,  Takanori Yokoyama ,  Nobuyasu Kanekawa

    IPC分类号： G06F3/00 ,  G06F13/00 ,  H04L7/00 ,  H04L29/06 ,  H04J3/06

    CPC分类号： G06F13/4291 ,  G06F9/54 ,  G06F13/102 ,  H04L12/40019 ,  H04L12/403 ,  H04L2012/40273

    摘要： A data communication system includes a master device, a plurality of slave devices, at least either a data transmission bus which connects the master device to a plurality of slave devices to transfer data from the master device to the slave devices in synchronism with a synchronous clock signal or a data reception bus over which the master device receives data from the slave devices in synchronism with a synchronous clock signal, and Chip Select signal lines which one-to-one connect the master device to the slave devices. The data communication system also includes communication drivers for setting a physical protocol of each slave device and a communication manager to arbitrate serial communications between the master device and the slave devices. The communication manager arbitrates serial communications to slave devices by their proper physical protocols. Communication protocols such as baud rates, clock polarities, and clock phases are switched by asserted Chip Select signal lines.

    摘要翻译： 数据通信系统包括主设备，多个从设备，至少一个数据传输总线，其将主设备连接到多个从设备，以与同步时钟同步地将数据从主设备传送到从设备 信号或数据接收总线，主设备通过该数据接收总线与同步时钟信号同步地从从设备接收数据，以及一对一将主设备连接到从设备的片选信号线。 数据通信系统还包括用于设置每个从设备的物理协议的通信驱动器和通信管理器来仲裁主设备和从设备之间的串行通信。 通信管理器通过其适当的物理协议仲裁到从设备的串行通信。 诸如波特率，时钟极性和时钟相位之类的通信协议由断言的片选信号线切换。

    Data communication system and controller
    5.
    发明申请
    Data communication system and controller 有权
    数据通信系统和控制器

    公开(公告)号：US20050172059A1

    公开(公告)日：2005-08-04

    申请号：US11016769

    申请日：2004-12-21

    申请人： Kentaro Yoshimura ,  Wataru Nagaura ,  Takanori Yokoyama ,  Nobuyasu Kanekawa

    发明人： Kentaro Yoshimura ,  Wataru Nagaura ,  Takanori Yokoyama ,  Nobuyasu Kanekawa

    IPC分类号： G06F13/38 ,  G06F13/10 ,  G06F13/42 ,  H04L12/40

    CPC分类号： G06F13/4291 ,  G06F9/54 ,  G06F13/102 ,  H04L12/40019 ,  H04L12/403 ,  H04L2012/40273

    摘要： A data communication system uses an SPI bus having a plurality of devices wherein data communications are enabled using communication protocols optimum to respective devices. The system includes a master device connected to a plurality of slave devices via a data transmission bus by which the master device transfers data to the slave devices, or a data reception bus by which the master device receives data from the slave devices, in a synchronism with a synchronous clock signal. Chip select signal lines also connect the master device to the slave devices, on a one to one basis. Communication drivers set a physical protocol of each slave device, and a communication manager arbitrates serial communications between the master device and the slave devices by their proper physical protocols. Communication protocols such as baud rates, clock polarities, and clock phases are switched by asserted Chip Select signal lines.

    摘要翻译： 数据通信系统使用具有多个设备的SPI总线，其中使用对各个设备最佳的通信协议来启用数据通信。 该系统包括：主设备经由数据传输总线连接到多个从设备的主设备，主设备通过该数据传输总线将数据传输到从设备，或者主设备通过该数据接收总线以同步方式从从设备接收数据 具有同步时钟信号。 芯片选择信号线还将主器件一对一连接到从器件。 通信驱动器设置每个从设备的物理协议，并且通信管理器通过其适当的物理协议来仲裁主设备和从设备之间的串行通信。 诸如波特率，时钟极性和时钟相位之类的通信协议由断言的片选信号线切换。

    Electronic controller for power converter and motor drive circuit
    6.
    发明授权
    Electronic controller for power converter and motor drive circuit 失效
    电源转换器和电机驱动电路的电子控制器

    公开(公告)号：US08131388B2

    公开(公告)日：2012-03-06

    申请号：US12482677

    申请日：2009-06-11

    申请人： Yuichiro Morita ,  Kotaro Shimamura ,  Kunihiko Tsunedomi ,  Shinya Imura ,  Shoji Sasaki ,  Takanori Yokoyama

    发明人： Yuichiro Morita ,  Kotaro Shimamura ,  Kunihiko Tsunedomi ,  Shinya Imura ,  Shoji Sasaki ,  Takanori Yokoyama

    IPC分类号： G06F1/26

    CPC分类号： G05B19/0423

    摘要： The electronic controller fetches an external signal and performs an input process such as A-D conversion. Upon receipt of processing results for executing operations according to a predetermined program, an output process is performed for sending a signal to the outside board on operation results, a timer outputs at least two of an input process start signal for starting the input process, an output process start signal for starting the output process, and an operation start signal for starting the operation.

    摘要翻译： 电子控制器提取外部信号，进行A-D转换等输入处理。 在接收到根据预定程序执行操作的处理结果时，执行用于在操作结果上向外部板发送信号的输出处理，定时器输出用于开始输入处理的输入处理开始信号中的至少两个， 用于开始输出处理的输出处理开始信号和用于开始操作的操作开始信号。

    Distributed computing system
    8.
    发明授权
    Distributed computing system 失效
    分布式计算系统

    公开(公告)号：US06578064B1

    公开(公告)日：2003-06-10

    申请号：US09167498

    申请日：1998-10-07

    申请人： Masahiko Saito ,  Takanori Yokoyama ,  Masaru Shimada ,  Kunihiko Tsunedomi ,  Tomoaki Nakamura

    发明人： Masahiko Saito ,  Takanori Yokoyama ,  Masaru Shimada ,  Kunihiko Tsunedomi ,  Tomoaki Nakamura

    IPC分类号： G06F900

    CPC分类号： G06F9/505 ,  G06F9/4862 ,  G06F9/5083 ,  G06F9/54 ,  G06F2209/5021 ,  H04L67/10

    摘要： A distributed computing system --,--; having a plurality of computers that differ from each other in terms of performance, load, and type, uniformly manages local priority schemes adapted in the respective computers by utilizing the concept of “urgency” or “time limit”. Each of the computers includes a priority level conversion procedure for performing a conversion between an urgency level and a priority level of processing in accordance with the performance and the load of the computer, and a priority level changing procedure for changing a priority level of a program, which executes the processing, in accordance with a priority level indicated by the priority level conversion procedure.

    摘要翻译： 分布式计算系统 - ， - ; 在性能，负载和类型方面具有彼此不同的多个计算机，通过利用“紧急”或“时间限制”的概念，统一管理在各个计算机中适应的本地优先级方案。 每个计算机包括根据计算机的性能和负载执行紧急度和优先级处理之间的转换的优先级转换过程，以及用于改变程序的优先级的优先级改变过程 ，其根据由优先级转换过程指示的优先级执行处理。

    Electronic Controller for Power Converter and Motor Drive Circuit
    9.
    发明申请
    Electronic Controller for Power Converter and Motor Drive Circuit 失效
    电力转换器和电机驱动电路电子控制器

    公开(公告)号：US20090248181A1

    公开(公告)日：2009-10-01

    申请号：US12482677

    申请日：2009-06-11

    申请人： Yuichiro MORITA ,  Kotaro Shimamura ,  Kunihiko Tsunedomi ,  Shinya Imura ,  Shoji Sasaki ,  Takanori Yokoyama

    发明人： Yuichiro MORITA ,  Kotaro Shimamura ,  Kunihiko Tsunedomi ,  Shinya Imura ,  Shoji Sasaki ,  Takanori Yokoyama

    IPC分类号： G06F1/26

    CPC分类号： G05B19/0423

    摘要： The electronic controller fetches an external signal and performs an input process such as A-D conversion. Upon receipt of processing results for executing operations according to a predetermined program, an output process is performed for sending a signal to the outside board on operation results, a timer outputs at least two of an input process start signal for starting the input process, an output process start signal for starting the output process, and an operation start signal for starting the operation.

    摘要翻译： 电子控制器提取外部信号，进行A-D转换等输入处理。 在接收到根据预定程序执行操作的处理结果时，执行用于在操作结果上向外部板发送信号的输出处理，定时器输出用于开始输入处理的输入处理开始信号中的至少两个， 用于开始输出处理的输出处理开始信号和用于开始操作的操作开始信号。