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25 条记录 (耗时 0.027 秒)

    Comparator circuit with variable hysteresis characteristic
    1.
    发明授权
    Comparator circuit with variable hysteresis characteristic 失效
    具有可变滞后特性的比较器电路

    公开(公告)号：US5166550A

    公开(公告)日：1992-11-24

    申请号：US635078

    申请日：1990-12-28

    申请人： Kunihiro Matsubara ,  Katsuya Shimizu

    发明人： Kunihiro Matsubara ,  Katsuya Shimizu

    IPC分类号： H03K5/00 ,  H03K3/0233

    CPC分类号： H03K3/02337

    摘要： A comparator circuit including a reference-voltage generating unit for generating a variable reference voltage, and a comparator having a first input terminal to which an input signal is supplied and a second input terminal to which the variable reference voltage from the reference-voltage generating unit is supplied. The comparator circuit also includes additional-voltage generating unit for generating an additional voltage that varies in proportion to the variable reference voltage, and a switching unit that is connected to the additional-voltage generating unit and activated or deactivated in response to an output of the comparator. When the switching unit is deactivated, the input signal is supplied to the first input terminal of the comparator and the variable reference voltage from the reference-voltage generating unit is supplied to the second input terminal of the comparator. When the switching unit is activated, the additional voltage from the additional-voltage generating unit is added to the input signal, and the sum of the input signal and the additional voltage is supplied to the first input terminal of the comparator so that an interpretation processing of the comparator is performed with a variable hysteresis characteristic corresponding to the additional voltage that varies in proportion to the variable reference voltage.

    摘要翻译： 一种比较器电路，包括用于产生可变参考电压的参考电压产生单元和具有提供输入信号的第一输入端的比较器和来自基准电压产生单元的可变参考电压的第二输入端 被提供。 比较器电路还包括用于产生与可变参考电压成比例地变化的附加电压的附加电压产生单元，以及连接到附加电压产生单元并且响应于所述可变参考电压的输出被激活或去激活的开关单元 比较器。 当切换单元被禁用时，输入信号被提供给比较器的第一输入端，并且来自基准电压产生单元的可变参考电压被提供给比较器的第二输入端。 当切换单元被激活时，来自附加电压产生单元的附加电压被加到输入信号上，并且输入信号和附加电压之和被提供给比较器的第一输入端，使得解释处理 以对应于与可变参考电压成比例变化的附加电压的可变滞后特性执行比较器。

    Photodiode Having Hetero-Junction Between Semi-Insulating Zinc Oxide Semiconductor Thin Film And Silicon
    4.
    发明申请
    Photodiode Having Hetero-Junction Between Semi-Insulating Zinc Oxide Semiconductor Thin Film And Silicon 审中-公开
    具有半绝缘氧化锌半导体薄膜和硅之间的杂环的光电二极管

    公开(公告)号：US20080116454A1

    公开(公告)日：2008-05-22

    申请号：US11795802

    申请日：2005-06-16

    申请人： Katsuya Shimizu

    发明人： Katsuya Shimizu

    IPC分类号： H01L31/0264

    CPC分类号： H01L31/109 ,  H01L31/1836 ,  Y02E10/50

    摘要： A photodiode which eliminates sensitivity reduction in a short wavelength region such as blue, an unavoidable problem posed by doping, resolves response reduction by the scattering of acceptor ions or impurities due to doping of impurities at the same time, and has very high sensitivity and fast response in a UV-IR range. A photodiode having a hetero-junction between a semi-insulating zinc oxide semiconductor thin film and silicon and comprising, basically, n-type silicon (1) and a semi-insulating zinc oxide semiconductor thin film (3) formed on the n-type silicon, characterized in that the n-type silicon forms a cathode region, and the formation of a semi-insulating zinc oxide semiconductor thin film produces a p-type inversion layer (4) at the upper portion of the n-type silicon in contact with the semi-insulating zinc oxide semiconductor thin film, the p-type inversion layer forming a photo-detection region and an anode region.

    摘要翻译： 消除诸如蓝色等短波长区域中的灵敏度降低的光电二极管，这是由掺杂引起的不可避免的问题，由于同时掺杂杂质而导致受体离子或杂质的散射引起的响应减小，并且具有非常高的灵敏度和快速 在UV-IR范围内的响应。 一种在半绝缘氧化锌半导体薄膜和硅之间具有异质结的光电二极管，其基本上包括n型硅（1）和形成在n型上的半绝缘氧化锌半导体薄膜（3） 硅，其特征在于，所述n型硅形成阴极区，并且半绝缘氧化锌半导体薄膜的形成在接触的n型硅的上部产生p型反型层（4） 与半绝缘氧化锌半导体薄膜，p型反型层形成光检测区域和阳极区域。

    Signal detection method, frequency detection method, power consumption control method, signal detecting device, frequency detecting device, power consumption control device and electronic apparatus
    6.
    发明申请
    Signal detection method, frequency detection method, power consumption control method, signal detecting device, frequency detecting device, power consumption control device and electronic apparatus 有权
    信号检测方法，频率检测方法，功耗控制方法，信号检测装置，频率检测装置，功耗控制装置和电子装置

    公开(公告)号：US20060156044A1

    公开(公告)日：2006-07-13

    申请号：US11122123

    申请日：2005-05-05

    申请人： Katsuya Shimizu ,  Hiroko Kinoshita

    发明人： Katsuya Shimizu ,  Hiroko Kinoshita

    IPC分类号： G06F1/26

    CPC分类号： G06F1/3203 ,  Y02D10/126

    摘要： A power consumption control device for detecting output of a pulse signal from an output terminal of an oscillator as an operation monitoring target and outputting a power consumption reduction signal when the pulse signal is not detected in a predetermined period of time, includes a p-type transistor and an n-type transistor which are connected in series and have a gate to which the output terminal is connected, and detecting means for detecting a through current flowing through the p-type transistor and n-type transistor, and outputs a power consumption reduction signal when the through current is not detected in a predetermined period of time.

    摘要翻译： 一种功率消耗控制装置，用于检测来自振荡器的输出端的脉冲信号的输出作为操作监视对象，并且当在预定时间段内未检测到脉冲信号时输出功耗降低信号，包括p型 晶体管和n型晶体管，其串联连接并具有连接有输出端子的栅极;以及检测装置，用于检测流过p型晶体管和n型晶体管的贯通电流，并输出功率消耗 在预定时间段内没有检测到通过电流时的减小信号。

    Multiplexer circuit having a simplified construction and reduced number of parts
    7.
    发明授权
    Multiplexer circuit having a simplified construction and reduced number of parts 失效
    多路复用器电路具有简化的结构和减少的部件数量

    公开(公告)号：US5189312A

    公开(公告)日：1993-02-23

    申请号：US705557

    申请日：1991-05-24

    申请人： Katsuya Shimizu ,  Tomoaki Ito

    发明人： Katsuya Shimizu ,  Tomoaki Ito

    IPC分类号： H03K17/00 ,  H03K17/62

    CPC分类号： H03K17/62

    摘要： A multiplexer circuit comprises a plurality of voltage generation circuits which produce corresponding output voltages having respective, different voltage levels in accordance with an ordered sequence thereof, from the lowest to the highest level. The outputs of the plurality of voltage generation circuits are supplied to a common output line. A decoder circuit receives a control data input signal which designates a selected one of the plurality of levels of the output signal and produces a signal for disabling each of the voltage generating circuits having an output voltage level of a higher order than that of the voltage generating circuit producing the output voltage of the selected level designated by the control data input signal. Voltage generating circuits of lower order need not be disabled.

    摘要翻译： 多路复用器电路包括多个电压产生电路，其根据其有序序列从最低到最高电平产生具有各自不同电压电平的相应输出电压。 多个电压产生电路的输出被提供给公共输出线。 解码器电路接收控制数据输入信号，该控制数据输入信号指定输出信号的多个电平中的所选择的一个电平，并产生用于禁用具有比产生电压的电压高的输出电压电平的每个电压发生电路的信号 产生由控制数据输入信号指定的选定电平的输出电压。 低阶电压发生电路不需要禁用。

    Power supply circuit for clamping excessive input voltage at predetermined voltage
    9.
    发明授权
    Power supply circuit for clamping excessive input voltage at predetermined voltage 失效
    用于在预定电压下钳制过大输入电压的电源电路

    公开(公告)号：US06667607B2

    公开(公告)日：2003-12-23

    申请号：US10107390

    申请日：2002-03-28

    申请人： Hiroshi Kawamura ,  Hidenobu Ito ,  Katsuya Shimizu ,  Hiroto Nakamichi

    发明人： Hiroshi Kawamura ,  Hidenobu Ito ,  Katsuya Shimizu ,  Hiroto Nakamichi

    IPC分类号： G05F304

    CPC分类号： G05F3/267

    摘要： A power supply circuit that withstands voltages greater than or equal to a voltage capacity and prevents an increase in circuit area and manufacturing costs. The power supply circuit includes a first transistor for receiving a DC voltage and generating an internal power supply voltage. A clamp circuit is connected to the first transistor. The clamp circuit is activated when the DC current voltage is an excessive voltage to clamp the internal power supply voltage at a predetermined voltage that is less than the excessive voltage. A gate voltage control circuit is connected to the first transistor and the clamp circuit to supply the gate of the transistor with a control voltage so that the internal power supply voltage decreases when the clamp circuit is activated.

    摘要翻译： 一种电源电路，其承受大于或等于电压容量的电压，并防止电路面积和制造成本的增加。 电源电路包括用于接收直流电压并产生内部电源电压的第一晶体管。 钳位电路连接到第一晶体管。 当直流电压是过大的电压时，钳位电路被激活，以将内部电源电压钳位在小于过电压的预定电压。 栅极电压控制电路连接到第一晶体管和钳位电路，以向晶体管的栅极提供控制电压，使得当钳位电路被激活时内部电源电压降低。

    Resin composition for printing plate
    10.
    发明授权
    Resin composition for printing plate 有权
    印版用树脂组合物

    公开(公告)号：US08129494B2

    公开(公告)日：2012-03-06

    申请号：US12521277

    申请日：2007-12-21

    申请人： Katsuya Shimizu

    发明人： Katsuya Shimizu

    IPC分类号： C08G64/00 ,  C08G63/02

    CPC分类号： C08F290/06 ,  B41C1/05 ,  B41N1/12 ,  C08F290/00 ,  C08F290/061 ,  C08F290/067 ,  C08G18/44 ,  C08G18/672 ,  C08G18/8116 ,  C08G64/0208 ,  C08G64/183 ,  C09D175/16 ,  G03F7/0007 ,  G03F7/038 ,  Y10T428/24479 ,  Y10T428/24628

    摘要： Disclosed is a polymer having excellent solvent resistance which can be produced by using a polycarbonate diol having a repeating unit represented by the formula (1) and/or (2), having a hydroxyl group at both termini, and having a number average molecular weight of from 300 to 50,000: wherein R1 represents a linear or branched hydrocarbon group having 2 to 50 carbon atoms; and n represents an integer of 2 to 50, wherein R2 represents a linear or branched hydrocarbon group having 10 to 50 carbon atoms.

    摘要翻译： 公开了一种具有优异的耐溶剂性的聚合物，其可以通过使用具有由式（1）和/或（2）表示的重复单元的聚碳酸酯二醇，其在两个末端具有羟基并具有数均分子量 为300〜50,000，式中，R1表示碳原子数2〜50的直链状或支链状的烃基。 n表示2〜50的整数，R表示碳原子数为10〜50的直链状或支链状的烃基。