公开(公告)号：US07321245B2

公开(公告)日：2008-01-22

申请号：US10808575

申请日：2004-03-25

申请人： Kuniyuki Tani ,  Atsushi Wada

发明人： Kuniyuki Tani ,  Atsushi Wada

IPC分类号： H03K3/00

CPC分类号： G11C5/145

摘要： A first bias voltage generating circuit which applies a bias voltage to an amplifier circuit of an AD converter has a driving unit and a control unit. The driving unit includes a first bias circuit and a second bias circuit as a plurality of bias circuits which are connected in parallel and have different current driving capabilities. The first bias circuit and the second bias circuit each include a CMOS transistor which is connected directly between a power supply potential and a ground potential, and a switching element which interrupts a feedthrough current. The drains of the CMOS transistors output the bias voltage. The control unit turns on both or either one of the first bias circuit and the second bias circuit, thereby controlling the current driving capability of the entire driving unit.

摘要翻译： 向AD转换器的放大电路施加偏置电压的第一偏置电压产生电路具有驱动单元和控制单元。 驱动单元包括第一偏置电路和第二偏置电路作为并联连接并具有不同电流驱动能力的多个偏置电路。 第一偏置电路和第二偏置电路各自包括直接连接在电源电位和接地电位之间的CMOS晶体管，以及中断馈通电流的开关元件。 CMOS晶体管的漏极输出偏置电压。 控制单元接通第一偏置电路和第二偏置电路中的任一个或任一个，从而控制整个驱动单元的电流驱动能力。

公开(公告)号：US07119729B2

公开(公告)日：2006-10-10

申请号：US11060306

申请日：2005-02-18

申请人： Atsushi Wada ,  Kuniyuki Tani ,  Shigeto Kobayashi

发明人： Atsushi Wada ,  Kuniyuki Tani ,  Shigeto Kobayashi

IPC分类号： H03M1/38

CPC分类号： H03M1/164 ,  H03M1/162

摘要： A first analog-digital converter circuit in a preceding stage converts an input analog signal into a digital value and retrieves the higher 4 bits. A second analog-digital converter circuit in a subsequent stage converts an input analog signal into a digital value and retrieves 3 bits including the 5th through 6th highest bits and a redundant bit, 3 bits including the 7th through 8th highest bits and a redundant bit, and 3 bits including the 9th through 10th highest bits and a redundant bit. Thus, the number of bits produced by conversion by the second analog-digital converter circuit in the subsequent stage of a cyclic type is configured to be smaller than the number of bits produced by conversion by the first analog-digital converter circuit in the preceding stage.

摘要翻译： 前一级的第一模数转换器电路将输入的模拟信号转换为数字值，并检索较高的4位。 后续阶段的第二模拟数字转换器电路将输入的模拟信号转换为数字值，并且检索包括第5至第6高位的3位和冗余位，包括第7位至第8位的3位和冗余位， 并且包括第9到第10最高位的3位和冗余位。 因此，通过第二模拟数字转换器电路在循环类型的后续阶段的转换而产生的位数被配置为小于由前一级中的第一模数转换器电路的转换产生的位数 。

公开(公告)号：US07088277B2

公开(公告)日：2006-08-08

申请号：US10945924

申请日：2004-09-22

申请人： Shigeto Kobayashi ,  Kuniyuki Tani ,  Atsushi Wada ,  Takafumi Nakamori

发明人： Shigeto Kobayashi ,  Kuniyuki Tani ,  Atsushi Wada ,  Takafumi Nakamori

IPC分类号： H03M1/12

CPC分类号： H03M1/06 ,  H03M1/162 ,  H03M1/365

摘要： A cyclic AD converter having a conversion processing speed or conversion accuracy designed no higher than necessary. In the AD converter, an input analog signal is held by a sample-and-hold circuit, and converted into a digital value by an AD conversion circuit. A DA conversion circuit converts the digital value output from the AD conversion circuit into an analog value. A subtractor circuit outputs the difference between the analog value output from the AD conversion circuit and the analog value held in the sample-and-hold circuit. An amplifier circuit amplifies the output of the subtractor circuit, and feeds back the resultant to the sample-and-hold circuit and the AD conversion circuit. In the course of this feedback-based cyclic processing, an amplification control circuit changes the gain of the amplifier circuit in accordance with the progress of the circulation.

摘要翻译： 一种循环AD转换器，其转换处理速度或转换精度设定为不必要。 在AD转换器中，输入模拟信号由采样保持电路保持，并由AD转换电路转换为数字值。 DA转换电路将从AD转换电路输出的数字值转换为模拟值。 减法器电路输出从AD转换电路输出的模拟值与保持在采样保持电路中的模拟值之间的差。 放大器电路放大减法器电路的输出，并将结果反馈到采样保持电路和AD转换电路。 在基于反馈的循环处理的过程中，放大控制电路根据循环的进行改变放大器电路的增益。

公开(公告)号：US07084803B2

公开(公告)日：2006-08-01

申请号：US11047706

申请日：2005-02-02

申请人： Shigeto Kobayashi ,  Kuniyuki Tani ,  Atsushi Wada

发明人： Shigeto Kobayashi ,  Kuniyuki Tani ,  Atsushi Wada

IPC分类号： H03M1/16 ,  H03M1/44

CPC分类号： H03M1/167 ,  H03M1/162

摘要： A first amplifier circuit amplifies an input signal by a factor of α. A first AD converter circuit is configured at an LSB voltage of VA and converts an input analog signal into a digital value of arbitrary N1 bits. A first DA converter circuit converts the digital value output from the first AD converter circuit into an analog signal. A subtracter circuit subtracts an output of the first DA converter circuit from an output of the first subtracter circuit. A second amplifier circuit amplifies an output of the subtracter circuit by a factor of β. A second AD converter is configured at an LSB voltage of VB and converts an input analog signal into a digital value of arbitrary N2 bits. In this circuit, the relation VA*α*β=VB*2N2 holds.

摘要翻译： 第一放大器电路以α的因子放大输入信号。 第一AD转换器电路配置为VA的LSB电压，并将输入的模拟信号转换成任意N 1位的数字值。 第一DA转换器电路将从第一AD转换器电路输出的数字值转换为模拟信号。 减法电路从第一减法器电路的输出中减去第一DA转换器电路的输出。 第二放大器电路将减法器电路的输出放大倍数为β。 第二AD转换器配置为VB的LSB电压，并将输入模拟信号转换为任意N 2位的数字值。 在该电路中，VA *α*β= VB * 2 N 2的关系成立。

公开(公告)号：US07002507B2

公开(公告)日：2006-02-21

申请号：US10945880

申请日：2004-09-22

申请人： Shigeto Kobayashi ,  Kuniyuki Tani ,  Atsushi Wada

发明人： Shigeto Kobayashi ,  Kuniyuki Tani ,  Atsushi Wada

IPC分类号： H03M1/14 ,  H03M1/40

CPC分类号： H03M1/1225 ,  H03M1/162 ,  H03M1/167

摘要： A need exists to provide an AD converter which is well balanced between an increase in processing speed and a decrease in circuit area. The AD converter performs an analog-to-digital conversion separately in four steps, while performing pipelined processing on an AD conversion of the first stage by a first AD conversion circuit and AD conversions of the second to fourth steps by a second AD conversion circuit. A DA conversion circuit, a subtractor circuit, and an amplifier circuit are utilized in a DA conversion, subtraction, and amplification in the first step as well as in DA conversions, subtractions, and amplifications in the second to fourth steps, thus shared in all the steps.

摘要翻译： 需要提供在处理速度的提高和电路面积的减小之间良好平衡的AD转换器。 AD转换器分四步执行模数转换，同时通过第一AD转换电路对第一级的AD转换进行流水线处理，并通过第二AD转换电路对第二至第四步进行AD转换。 在第一步中的DA转换，减法和放大以及第二至第四步中的DA转换，减法和放大中都使用DA转换电路，减法器电路和放大器电路，因此共享 步骤。

公开(公告)号：US20050174277A1

公开(公告)日：2005-08-11

申请号：US11052093

申请日：2005-02-08

申请人： Kuniyuki Tani ,  Atsushi Wada ,  Shigeto Kobayashi

发明人： Kuniyuki Tani ,  Atsushi Wada ,  Shigeto Kobayashi

IPC分类号： H03M1/16 ,  H03M1/34 ,  H03M1/12

CPC分类号： H03M1/167 ,  H03M1/162

摘要： A first amplifier circuit samples and holds an input analog signal and outputs the same to a subtracting circuit. An AD converter circuit converts the input analog signal into a digital value so as to retrieve a predetermined number of bits. A DA converter circuit converts the digital value derived from conversion by the AD converter circuit into an analog value. A subtracter circuit subtracts an output analog signal from the DA converter circuit from the analog signal input via a first switch or the first amplifier circuit. A second amplifier circuit amplifies an output analog signal from the subtracter circuit by a gain of 2 and outputs the amplified signal. An input switching circuit controls the order of inputs, i.e. the input analog signal and a reference voltage, to voltage comparison elements constituting the Ad converter circuit.

摘要翻译： 第一放大器电路对输入的模拟信号进行采样并保持，并将其输出到减法电路。 AD转换器电路将输入的模拟信号转换为数字值，以便检索预定数量的位。 DA转换器电路将由AD转换器电路的转换得到的数字值转换为模拟值。 减法电路经由第一开关或第一放大器电路从DA转换器电路的模拟信号输入中减去输出模拟信号。 第二放大器电路将来自减法器电路的输出模拟信号以2的增益放大并输出放大的信号。 输入开关电路将输入的顺序，即输入模拟信号和参考电压控制到构成Ad转换器电路的电压比较元件。

公开(公告)号：US06696680B2

公开(公告)日：2004-02-24

申请号：US10358310

申请日：2003-02-05

申请人： Atsushi Wada ,  Takeshi Otsuka ,  Kuniyuki Tani

发明人： Atsushi Wada ,  Takeshi Otsuka ,  Kuniyuki Tani

IPC分类号： H01J4014

CPC分类号： G06G7/28 ,  H03G1/0088

摘要： A variable resistance circuit comprises a resistance circuit including a plurality of resistors serially connected, and a bypass circuit connected in parallel with the resistance circuit for bypassing one or more resistors selected from the plurality of resistors. The bypass circuit includes a plurality of transistors selectively turned on or off. The variable resistance value is determined by a combined resistance value of a parasitic resistance of one or more transistors being turned on and one or more resistors being bypassed as well as a combined resistance value of one or more resistors being not bypassed. The gate widths of the plurality of transistors are so set that the variable resistance value varies approximately in steps of a predetermined value. Various resistance values can be set in high precision by selectively turning on or off the plurality of transistors.

摘要翻译： 可变电阻电路包括包括串联连接的多个电阻器的电阻电路和与电阻电路并联连接的旁路电路，用于旁路从多个电阻器中选择的一个或多个电阻器。 旁路电路包括选择性地导通或关断的多个晶体管。 可变电阻值由导通的一个或多个晶体管的寄生电阻和被旁路的一个或多个电阻器的组合电阻值以及不绕过的一个或多个电阻器的组合电阻值确定。 多个晶体管的栅极宽度被设定为可变电阻值以预定值的步长近似变化。 通过选择性地打开或关闭多个晶体管，可以高精度地设置各种电阻值。

公开(公告)号：US07745776B2

公开(公告)日：2010-06-29

申请号：US11864286

申请日：2007-09-28

申请人： Atsushi Wada ,  Kuniyuki Tani ,  Hajime Takashima

发明人： Atsushi Wada ,  Kuniyuki Tani ,  Hajime Takashima

IPC分类号： H01L31/062

CPC分类号： H04N5/235 ,  H04N5/335 ,  H04N5/35509 ,  H04N5/374 ,  H04N5/37452

摘要： In a photo detecting apparatus, a first capacitance is caused by a photo detecting element and the first capacitance is charged or discharged by current flowing through the photo detecting element. A second capacitance is connected in parallel with the photo detecting element, and the second capacitance charges or discharges an electric charge overflowing from the first capacitance. A current control element is connected to a terminal of the second capacitance on a side where the electric charge flows in, and the current control element delivers a current to cancel part of an electric charge when the electric charge overflowing from the first capacitance is stored in the second capacitance.

摘要翻译： 在光检测装置中，由光检测元件引起第一电容，并且通过流过光检测元件的电流对第一电容进行充电或放电。 第二电容与光检测元件并联连接，第二电容对从第一电容溢出的电荷进行充电或放电。 电流控制元件连接到电荷流入侧的第二电容的端子，并且当从第一电容溢出的电荷被存储在电流控制元件中时，电流控制元件输出电流以消除部分电荷 第二电容。

公开(公告)号：US20080067325A1

公开(公告)日：2008-03-20

申请号：US11858583

申请日：2007-09-20

申请人： Kuniyuki Tani ,  Hajime Takashima ,  Atsushi Wada

发明人： Kuniyuki Tani ,  Hajime Takashima ,  Atsushi Wada

IPC分类号： H01L27/144

CPC分类号： H04N5/235 ,  H01L27/14609 ,  H01L27/14621 ,  H01L27/14656 ,  H04N5/3559 ,  H04N5/3591 ,  H04N5/3594 ,  H04N5/374

摘要： A plurality of pixel circuits, provided with a plurality of photo detecting elements, respectively, cause photocurrent corresponding to an incident light. The pixel circuits are placed on intersections of a plurality of data lines and scanning lines, respectively. A second capacitance charges and discharges an electric charge overflowing from a first capacitance caused by the photo detecting element. Each second capacitance is shared by a plurality of pixel circuits. A plurality of pixel circuits sharing the second capacitance are controlled so that exposure periods of the pixel circuits do not overlap with one another.

摘要翻译： 分别具有多个光检测元件的多个像素电路分别引起与入射光对应的光电流。 像素电路分别放置在多条数据线和扫描线的交点上。 第二电容对由光检测元件引起的第一电容溢出的电荷进行放电。 每个第二电容由多个像素电路共享。 控制共享第二电容的多个像素电路，使得像素电路的曝光周期彼此不重叠。

公开(公告)号：US20070109174A1

公开(公告)日：2007-05-17

申请号：US11651018

申请日：2007-01-09

申请人： Shigeto Kobayashi ,  Atsushi Wada ,  Kuniyuki Tani

发明人： Shigeto Kobayashi ,  Atsushi Wada ,  Kuniyuki Tani

IPC分类号： H03M1/12

CPC分类号： H03M1/1225 ,  H03M1/167

摘要： One or more input capacitors are connected to an inverting input terminal of an operational amplifier. Connected to the respective input capacitors are switches for on-off control of the input of an input signal, switches for on-off control of the input of another input signal, switches for on-off control of the input of a higher reference voltage and switches for on-off control of the input of a lower reference voltage. The switches for on-off control of the input of an input signal and the switches for on-off control of the input of another input signal are controlled by independent control signals.

摘要翻译： 一个或多个输入电容器连接到运算放大器的反相输入端。 连接到各个输入电容器的开关用于对输入信号的输入进行开关控制，用于开关控制另一个输入信号的输入，用于开关控制更高参考电压的输入，以及 用于开关控制较低参考电压的输入。 用于对输入信号的输入的开关控制的开关和用于另一个输入信号的输入的开关控制的开关由独立的控制信号控制。