公开(公告)号：US20130062785A1

公开(公告)日：2013-03-14

申请号：US13612867

申请日：2012-09-13

Applicant: Kuo-Fan Lin ,  Chi-Shang Lin

Inventor： Kuo-Fan Lin ,  Chi-Shang Lin

IPC: H01L23/498 ,  H01L21/56

CPC classification number: H01L23/4952 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/49562 ,  H01L23/498 ,  H01L23/62 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/16 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/13111 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/16106 ,  H01L2224/16245 ,  H01L2224/29339 ,  H01L2224/32013 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48247 ,  H01L2224/49107 ,  H01L2224/49113 ,  H01L2224/73265 ,  H01L2924/12035 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A transistor structure includes a chip package and two pins, wherein the chip package includes a transistor die and a molding compound encapsulating the transistor die. One of the pins is electrically connected to a first bonding pad and a second bonding pad of the transistor die, and another of the pins is electrically connected to a third bonding pad of the transistor die. The transistor structure may be employed in a snubber circuit to connect an active component or a load in parallel to absorb spikes or noise generated by the active component while the active component is switching at a high frequency. Therefore, the packaging of the transistor structure could simplify the process, reduce size, increase the withstanding voltage, and improve the efficiency and reduce the spike voltage of the power supply of the snubber circuit.

Abstract translation: 晶体管结构包括芯片封装和两个引脚，其中芯片封装包括晶体管管芯和封装晶体管管芯的模制化合物。 一个引脚电连接到晶体管管芯的第一焊盘和第二接合焊盘，另一个引脚电连接到晶体管管芯的第三焊盘。 晶体管结构可以用在缓冲电路中以平行地连接有源部件或负载，以吸收由有源部件在高频率切换时由有源部件产生的尖峰或噪声。 因此，晶体管结构的封装可以简化工艺，减小尺寸，增加耐受电压，提高效率，降低缓冲电路电源的尖峰电压。