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    Microelectromechanical device manufacturing process
    2.
    发明授权
    Microelectromechanical device manufacturing process 失效
    微机电装置制造工艺

    公开(公告)号：US06337027B1

    公开(公告)日：2002-01-08

    申请号：US09410166

    申请日：1999-09-30

    Applicant: Kurt D. Humphrey

    Inventor： Kurt D. Humphrey

    IPC: H01L2100

    CPC classification number: B81C1/00928 ,  B81C1/00849 ,  B81C2201/0138 ,  B81C2201/019

    Abstract: The present invention relates to micro electromechanical systems (MEMS) devices and more specifically to a process for manufacturing MEMS devices having at least one suspended structural element. The present invention seeks to provide an improved method for manufacture of MEMS devices having improved safety and increased yield and throughput compared to conventional EDP immersion process techniques. MEMS devices are made using a modified dissolution process that removes, in a selective etch step, inactive silicon to release an active silicon device from a sacrificial substrate. The present invention uses a selective etchant in conjunction with a commercial spray acid processing tool to provide a dissolution process with improved throughput, improved repeatable and uniform etch rates and reduction in the number of processing steps and chemical containment for improved safety. When the etch process is complete, the solvent spray is turned off and a spray of de-ionized water is directed onto composite structure to remove residual solvent without causing suspended elements to adhere to the support substrate.

    Abstract translation: 本发明涉及微机电系统（MEMS）装置，更具体地涉及一种用于制造具有至少一个悬挂结构元件的MEMS装置的方法。 本发明寻求提供一种用于制造具有改进的安全性并且与常规EDP浸渍工艺技术相比增加的产量和产量的MEMS装置的改进方法。 使用改进的溶解过程制造MEMS器件，其在选择性蚀刻步骤中去除非活性硅以从牺牲衬底释放活性硅器件。 本发明使用选择性蚀刻剂与商业喷雾酸处理工具结合，以提供具有改善的生产量，改进的可重复和均匀蚀刻速率的溶解过程以及减少加工步骤和化学容纳物以提高安全性。 当蚀刻过程完成时，关闭溶剂喷雾，并将去离子水的喷雾引导到复合结构上以除去残留的溶剂，而不会使悬浮的元素粘附到载体基底上。

    Method of forming high speed, high voltage fully isolated bipolar transistors on a SOI substrate
    3.
    发明授权
    Method of forming high speed, high voltage fully isolated bipolar transistors on a SOI substrate 失效
    在SOI衬底上形成高速，高电压全隔离双极晶体管的方法

    公开(公告)号：US5344785A

    公开(公告)日：1994-09-06

    申请号：US72653

    申请日：1993-06-03

    Applicant: Rick C. Jerome ,  Diane R. Williams ,  Kurt D. Humphrey

    Inventor： Rick C. Jerome ,  Diane R. Williams ,  Kurt D. Humphrey

    IPC: H01L21/331 ,  H01L21/762 ,  H01L27/082 ,  H01L21/265

    CPC classification number: H01L29/66265 ,  H01L21/76235 ,  H01L27/082 ,  Y10S148/085 ,  Y10S148/15

    Abstract: A method of manufacturing various types of silicon devices, such as complementary bipolar PNP and NPN transistors, in a Silicon On Insulator ("SOI") Integrated Circuit ("IC"), the SOI IC having a substrate, a buried insulating layer disposed above the substrate, and a silicon device layer disposed above the insulating layer. Vertical transistors may be formed in the device layer such that each transistor is fully dielectrically isolated from another and also from other similarly manufactured silicon devices in the silicon device layer.

    Abstract translation: 在硅绝缘体（“SOI”）集成电路（“IC”）中制造各种类型的硅器件（例如互补双极性PNP和NPN晶体管）的方法，具有衬底的SOI IC，设置在上面的掩埋绝缘层 衬底和设置在绝缘层上方的硅器件层。 可以在器件层中形成垂直晶体管，使得每个晶体管完全介电地与另一晶体管隔离，也可以与硅器件层中的其它类似制造的硅器件完全介电隔离。

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