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公开(公告)号:US20080273405A1
公开(公告)日:2008-11-06
申请号:US11896349
申请日:2007-08-31
申请人: Sung-Jae Byun , Dong Hyuk Chae , Kyoung Lae Cho , Jun Jin Kong , Young Hwan Lee , Seung Jae Lee , Nam Phil Jo , Dong Ku Kang
发明人: Sung-Jae Byun , Dong Hyuk Chae , Kyoung Lae Cho , Jun Jin Kong , Young Hwan Lee , Seung Jae Lee , Nam Phil Jo , Dong Ku Kang
IPC分类号: G11C7/00
CPC分类号: G11C11/5628 , G11C2211/5621 , G11C2211/5641
摘要: A multi-bit programming device and method for a non-volatile memory are provided. In one example embodiment, a multi-bit programming device may include a multi-bit programming unit configured to multi-bit program original multi-bit data to a target memory cell in a memory cell array, and a backup programming unit configured to select backup memory cells in the memory cell array with respect to each bit of the original multi-bit data, and program each bit of the original multi-bit data to a respective one of the selected backup memory cells.
摘要翻译: 提供了一种用于非易失性存储器的多位编程设备和方法。 在一个示例实施例中,多位编程设备可以包括多位编程单元,其被配置为将原始多位数据多位地编程到存储单元阵列中的目标存储器单元,以及备份编程单元,被配置为选择备份 相对于原始多位数据的每个位存储单元阵列中的存储器单元,以及将原始多位数据的每个位编程到所选择的备份存储器单元中的相应一个。
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2.
公开(公告)号:US07706181B2
公开(公告)日:2010-04-27
申请号:US11896349
申请日:2007-08-31
申请人: Sung-Jae Byun , Dong Hyuk Chae , Kyoung Lae Cho , Jun Jin Kong , Young Hwan Lee , Seung Jae Lee , Nam Phil Jo , Dong Ku Kang
发明人: Sung-Jae Byun , Dong Hyuk Chae , Kyoung Lae Cho , Jun Jin Kong , Young Hwan Lee , Seung Jae Lee , Nam Phil Jo , Dong Ku Kang
CPC分类号: G11C11/5628 , G11C2211/5621 , G11C2211/5641
摘要: A multi-bit programming device and method for a non-volatile memory are provided. In one example embodiment, a multi-bit programming device may include a multi-bit programming unit configured to multi-bit program original multi-bit data to a target memory cell in a memory cell array, and a backup programming unit configured to select backup memory cells in the memory cell array with respect to each bit of the original multi-bit data, and program each bit of the original multi-bit data to a respective one of the selected backup memory cells.
摘要翻译: 提供了一种用于非易失性存储器的多位编程设备和方法。 在一个示例实施例中,多位编程设备可以包括多位编程单元,其被配置为将原始多位数据多位地编程到存储单元阵列中的目标存储器单元,以及备份编程单元,被配置为选择备份 相对于原始多位数据的每个位存储单元阵列中的存储器单元,以及将原始多位数据的每个位编程到所选择的备份存储器单元中的相应一个。
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公开(公告)号:US07751239B2
公开(公告)日:2010-07-06
申请号:US11907082
申请日:2007-10-09
申请人: Kyoung Lae Cho , Jun Jin Kong , Dong Hyuk Chae , Seung Jae Lee , Sung-Jae Byun , Dong Ku Kang
发明人: Kyoung Lae Cho , Jun Jin Kong , Dong Hyuk Chae , Seung Jae Lee , Sung-Jae Byun , Dong Ku Kang
IPC分类号: G11C11/34
CPC分类号: G11C11/5642
摘要: Provided are a device for reading memory data and a method using the same. The device for reading memory data comprises a memory cell which stores multi-bit information, an information detection unit which detects as much bit information as a predetermined number of bits from among multi-bit information, a source-line voltage control unit which controls a source-line voltage of the memory cell based on the detected bit information from the information detection unit, and a remaining bit information read unit which reads remaining bit information stored in the memory cell by using the controlled source-line voltage.
摘要翻译: 提供了用于读取存储器数据的装置和使用其的方法。 用于读取存储器数据的装置包括存储多位信息的存储单元,从多位信息中检测多达位数信息作为预定位数的信息检测单元,控制位 基于来自信息检测单元的检测到的比特信息的存储器单元的源极线电压以及通过使用受控的源极线电压读取存储在存储器单元中的剩余位信息的剩余位信息读取单元。
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公开(公告)号:US20090196097A1
公开(公告)日:2009-08-06
申请号:US11907082
申请日:2007-10-09
申请人: Kyoung Lae Cho , Jun Jin Kong , Dong Hyuk Chae , Seung Jae Lee , Sung-Jae Byun , Dong Ku Kang
发明人: Kyoung Lae Cho , Jun Jin Kong , Dong Hyuk Chae , Seung Jae Lee , Sung-Jae Byun , Dong Ku Kang
CPC分类号: G11C11/5642
摘要: Provided are a device for reading memory data and a method using the same. The device for reading memory data comprises a memory cell which stores multi-bit information, an information detection unit which detects as much bit information as a predetermined number of bits from among multi-bit information, a source-line voltage control unit which controls a source-line voltage of the memory cell based on the detected bit information from the information detection unit, and a remaining bit information read unit which reads remaining bit information stored in the memory cell by using the controlled source-line voltage.
摘要翻译: 提供了用于读取存储器数据的装置和使用其的方法。 用于读取存储器数据的装置包括存储多位信息的存储单元,从多位信息中检测多达位数信息作为预定位数的信息检测单元,控制位 基于来自信息检测单元的检测到的比特信息的存储器单元的源极线电压以及通过使用受控的源极线电压读取存储在存储器单元中的剩余位信息的剩余位信息读取单元。
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公开(公告)号:US08112693B2
公开(公告)日:2012-02-07
申请号:US11905734
申请日:2007-10-03
申请人: Jun Jin Kong , Seung-Hwan Song , Dong Hyuk Chae , Kyoung Lae Cho , Seung Jae Lee , Nam Phil Jo , Sung Chung Park , Dong Ku Kang
发明人: Jun Jin Kong , Seung-Hwan Song , Dong Hyuk Chae , Kyoung Lae Cho , Seung Jae Lee , Nam Phil Jo , Sung Chung Park , Dong Ku Kang
IPC分类号: G11C29/00
CPC分类号: G06F11/1072
摘要: An Error Control Code (ECC) apparatus applied to a memory of a Multi-Level Cell (MLC) method may include: a bypass control signal generator generating a bypass control signal; and an ECC performing unit that may include at least two ECC decoding blocks, determining whether to bypass a portion of the at least two ECC decoding blocks based on the bypass control signal, and/or performing an ECC decoding. In addition or in the alternative, the ECC performing unit may include at least two ECC encoding blocks, determining whether to bypass a portion of the at least two ECC encoding blocks based on the bypass control signal, and/or performing an ECC encoding. An ECC method applied to a memory of a MLC method and a computer-readable recording medium storing a program for implementing an EEC method applied to a memory of a MLC method are also disclose.
摘要翻译: 应用于多电平单元(MLC)方法的存储器的错误控制码(ECC)装置可以包括:旁路控制信号发生器,其生成旁路控制信号; 以及ECC执行单元,其可以包括至少两个ECC解码块,基于旁路控制信号确定是否绕过所述至少两个ECC解码块的一部分,和/或执行ECC解码。 另外或在替代方案中,ECC执行单元可以包括至少两个ECC编码块,基于旁路控制信号确定是否绕过至少两个ECC编码块的一部分,和/或执行ECC编码。 还公开了应用于MLC方法的存储器的ECC方法和存储用于实现应用于MLC方法的存储器的EEC方法的程序的计算机可读记录介质。
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公开(公告)号:US20080276149A1
公开(公告)日:2008-11-06
申请号:US11905733
申请日:2007-10-03
申请人: Jun Jin Kong , Seung-Hwan Song , Young Hwan Lee , Dong Hyuk Chae , Kyoung Lae Cho , Nam Phil Jo , Sung Chung Park , Dong Ku Kang
发明人: Jun Jin Kong , Seung-Hwan Song , Young Hwan Lee , Dong Hyuk Chae , Kyoung Lae Cho , Nam Phil Jo , Sung Chung Park , Dong Ku Kang
IPC分类号: G06F11/07
CPC分类号: G06F11/1008
摘要: An Error Control Code (ECC) apparatus may include a control signal generator that generates an ECC control signal based on channel information. The ECC apparatus also may include: a plurality of ECC encoding controllers that output data respectively inputted via storage elements corresponding to the ECC control signal; and/or an encoding unit that encodes, using a plurality of data outputted from the plurality of ECC encoding controllers, encoding input data into a number of subdata corresponding to the ECC control signal. In addition or in the alternative, the ECC apparatus may include: a plurality of ECC decoding controllers that output data respectively inputted via the storage elements corresponding to the ECC control signal; and/or a decoding unit that decodes, using a plurality of data outputted from the plurality of ECC decoding controllers, a number of decoding input data corresponding to the ECC control signal into one piece of output data.
摘要翻译: 错误控制码(ECC)装置可以包括基于频道信息产生ECC控制信号的控制信号发生器。 ECC装置还可以包括:多个ECC编码控制器,其输出经由与ECC控制信号对应的存储元件分别输入的数据; 和/或编码单元,其使用从所述多个ECC编码控制器输出的多个数据,将输入数据编码为对应于所述ECC控制信号的多个子数据进行编码。 另外或者可选地,ECC装置可以包括:多个ECC解码控制器,其输出经由与ECC控制信号对应的存储元件分别输入的数据; 和/或解码单元,其使用从所述多个ECC解码控制器输出的多个数据将对应于所述ECC控制信号的多个解码输入数据解码为一条输出数据。
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公开(公告)号:US20080285340A1
公开(公告)日:2008-11-20
申请号:US12007921
申请日:2008-01-17
申请人: Seung-Hwan Song , Jun Jin Kong , Sung Chung Park , Dong Hyuk Chae , Seung Jae Lee , Dong Ku Kang
发明人: Seung-Hwan Song , Jun Jin Kong , Sung Chung Park , Dong Hyuk Chae , Seung Jae Lee , Dong Ku Kang
CPC分类号: G11C16/26 , G11C7/1006 , G11C11/5642
摘要: Disclosed are an apparatus and a method for reading data. The method for reading data according to example embodiments includes comparing a threshold voltage of a memory cell with a first boundary voltage, comparing the threshold voltage with a second boundary voltage having a higher voltage level than that of the first boundary voltage, and determining data of the memory cell based on the threshold voltage, the first boundary voltage, and the second boundary voltage.
摘要翻译: 公开了一种用于读取数据的装置和方法。 根据示例实施例的用于读取数据的方法包括将存储器单元的阈值电压与第一边界电压进行比较,将阈值电压与具有比第一边界电压的电压电平更高的电压电平的第二边界电压进行比较,以及确定数据 所述存储单元基于所述阈值电压,所述第一边界电压和所述第二边界电压。
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公开(公告)号:US07800954B2
公开(公告)日:2010-09-21
申请号:US12007921
申请日:2008-01-17
申请人: Seung-Hwan Song , Jun Jin Kong , Sung Chung Park , Dong Hyuk Chae , Seung Jae Lee , Dong Ku Kang
发明人: Seung-Hwan Song , Jun Jin Kong , Sung Chung Park , Dong Hyuk Chae , Seung Jae Lee , Dong Ku Kang
IPC分类号: G11C11/34
CPC分类号: G11C16/26 , G11C7/1006 , G11C11/5642
摘要: The method for reading data according to example embodiments includes comparing a threshold voltage of a memory cell with a first boundary voltage, comparing the threshold voltage with a second boundary voltage having a higher voltage level than that of the first boundary voltage, and determining data of the memory cell based on the threshold voltage, the first boundary voltage, and the second boundary voltage.
摘要翻译: 根据示例实施例的用于读取数据的方法包括将存储器单元的阈值电压与第一边界电压进行比较,将阈值电压与具有比第一边界电压的电压电平更高的电压电平的第二边界电压进行比较,以及确定数据 所述存储单元基于所述阈值电压,所述第一边界电压和所述第二边界电压。
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公开(公告)号:US08028215B2
公开(公告)日:2011-09-27
申请号:US11905733
申请日:2007-10-03
申请人: Jun Jin Kong , Seung-Hwan Song , Young Hwan Lee , Dong Hyuk Chae , Kyong Lae Cho , Nam Phil Jo , Sung Chung Park , Dong Ku Kang
发明人: Jun Jin Kong , Seung-Hwan Song , Young Hwan Lee , Dong Hyuk Chae , Kyong Lae Cho , Nam Phil Jo , Sung Chung Park , Dong Ku Kang
CPC分类号: G06F11/1008
摘要: An Error Control Code (ECC) apparatus may include a control signal generator that generates an ECC control signal based on channel information. The ECC apparatus also may include: a plurality of ECC encoding controllers that output data respectively inputted via storage elements corresponding to the ECC control signal; and/or an encoding unit that encodes, using a plurality of data outputted from the plurality of ECC encoding controllers, encoding input data into a number of subdata corresponding to the ECC control signal. In addition or in the alternative, the ECC apparatus may include: a plurality of ECC decoding controllers that output data respectively inputted via the storage elements corresponding to the ECC control signal; and/or a decoding unit that decodes, using a plurality of data outputted from the plurality of ECC decoding controllers, a number of decoding input data corresponding to the ECC control signal into one piece of output data.
摘要翻译: 错误控制码(ECC)装置可以包括基于频道信息产生ECC控制信号的控制信号发生器。 ECC装置还可以包括:多个ECC编码控制器,其输出经由与ECC控制信号对应的存储元件分别输入的数据; 和/或编码单元,其使用从所述多个ECC编码控制器输出的多个数据,将输入数据编码为对应于所述ECC控制信号的多个子数据进行编码。 另外或者可选地,ECC装置可以包括:多个ECC解码控制器,其输出经由与ECC控制信号对应的存储元件分别输入的数据; 和/或解码单元,其使用从所述多个ECC解码控制器输出的多个数据将对应于所述ECC控制信号的多个解码输入数据解码为一条输出数据。
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10.
公开(公告)号:US20090103360A1
公开(公告)日:2009-04-23
申请号:US12255211
申请日:2008-10-21
申请人: Dong Ku Kang , Dong-Hyuk Chae , Seung-Jae Lee
发明人: Dong Ku Kang , Dong-Hyuk Chae , Seung-Jae Lee
CPC分类号: G11C16/10 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/3418 , G11C2211/5646
摘要: The flash memory device of the present invention is configured to program a plurality of bits per unit cell, wherein a program condition of a selected bit is set according to whether a program for the most previous bit to the selected bit for programming is skipped or not skipped. As a result, an accurate programming and reading operation is possible even in case a program for a middle bit is skipped.
摘要翻译: 本发明的闪速存储器件被配置为对每个单位单元的多个位进行编程,其中根据用于编程的选择位的最前一位的程序是否被跳过来设置所选位的程序状态 跳过 因此,即使在中间位的程序被跳过的情况下也可以进行准确的编程和读取操作。
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