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    Error control code apparatuses and methods of using the same
    3.
    发明授权
    Error control code apparatuses and methods of using the same 有权
    错误控制代码设备及其使用方法

    公开(公告)号：US08112693B2

    公开(公告)日：2012-02-07

    申请号：US11905734

    申请日：2007-10-03

    申请人： Jun Jin Kong ,  Seung-Hwan Song ,  Dong Hyuk Chae ,  Kyoung Lae Cho ,  Seung Jae Lee ,  Nam Phil Jo ,  Sung Chung Park ,  Dong Ku Kang

    发明人： Jun Jin Kong ,  Seung-Hwan Song ,  Dong Hyuk Chae ,  Kyoung Lae Cho ,  Seung Jae Lee ,  Nam Phil Jo ,  Sung Chung Park ,  Dong Ku Kang

    IPC分类号： G11C29/00

    CPC分类号： G06F11/1072

    摘要： An Error Control Code (ECC) apparatus applied to a memory of a Multi-Level Cell (MLC) method may include: a bypass control signal generator generating a bypass control signal; and an ECC performing unit that may include at least two ECC decoding blocks, determining whether to bypass a portion of the at least two ECC decoding blocks based on the bypass control signal, and/or performing an ECC decoding. In addition or in the alternative, the ECC performing unit may include at least two ECC encoding blocks, determining whether to bypass a portion of the at least two ECC encoding blocks based on the bypass control signal, and/or performing an ECC encoding. An ECC method applied to a memory of a MLC method and a computer-readable recording medium storing a program for implementing an EEC method applied to a memory of a MLC method are also disclose.

    摘要翻译： 应用于多电平单元（MLC）方法的存储器的错误控制码（ECC）装置可以包括：旁路控制信号发生器，其生成旁路控制信号; 以及ECC执行单元，其可以包括至少两个ECC解码块，基于旁路控制信号确定是否绕过所述至少两个ECC解码块的一部分，和/或执行ECC解码。 另外或在替代方案中，ECC执行单元可以包括至少两个ECC编码块，基于旁路控制信号确定是否绕过至少两个ECC编码块的一部分，和/或执行ECC编码。 还公开了应用于MLC方法的存储器的ECC方法和存储用于实现应用于MLC方法的存储器的EEC方法的程序的计算机可读记录介质。

    Error control code apparatuses and methods of using the same
    4.
    发明申请
    Error control code apparatuses and methods of using the same 有权
    错误控制代码设备及其使用方法

    公开(公告)号：US20080276149A1

    公开(公告)日：2008-11-06

    申请号：US11905733

    申请日：2007-10-03

    申请人： Jun Jin Kong ,  Seung-Hwan Song ,  Young Hwan Lee ,  Dong Hyuk Chae ,  Kyoung Lae Cho ,  Nam Phil Jo ,  Sung Chung Park ,  Dong Ku Kang

    发明人： Jun Jin Kong ,  Seung-Hwan Song ,  Young Hwan Lee ,  Dong Hyuk Chae ,  Kyoung Lae Cho ,  Nam Phil Jo ,  Sung Chung Park ,  Dong Ku Kang

    IPC分类号： G06F11/07

    CPC分类号： G06F11/1008

    摘要： An Error Control Code (ECC) apparatus may include a control signal generator that generates an ECC control signal based on channel information. The ECC apparatus also may include: a plurality of ECC encoding controllers that output data respectively inputted via storage elements corresponding to the ECC control signal; and/or an encoding unit that encodes, using a plurality of data outputted from the plurality of ECC encoding controllers, encoding input data into a number of subdata corresponding to the ECC control signal. In addition or in the alternative, the ECC apparatus may include: a plurality of ECC decoding controllers that output data respectively inputted via the storage elements corresponding to the ECC control signal; and/or a decoding unit that decodes, using a plurality of data outputted from the plurality of ECC decoding controllers, a number of decoding input data corresponding to the ECC control signal into one piece of output data.

    摘要翻译： 错误控制码（ECC）装置可以包括基于频道信息产生ECC控制信号的控制信号发生器。 ECC装置还可以包括：多个ECC编码控制器，其输出经由与ECC控制信号对应的存储元件分别输入的数据; 和/或编码单元，其使用从所述多个ECC编码控制器输出的多个数据，将输入数据编码为对应于所述ECC控制信号的多个子数据进行编码。 另外或者可选地，ECC装置可以包括：多个ECC解码控制器，其输出经由与ECC控制信号对应的存储元件分别输入的数据; 和/或解码单元，其使用从所述多个ECC解码控制器输出的多个数据将对应于所述ECC控制信号的多个解码输入数据解码为一条输出数据。

    Device for reading memory data and method using the same
    5.
    发明授权
    Device for reading memory data and method using the same 有权
    用于读取存储器数据的装置和使用其的方法

    公开(公告)号：US07751239B2

    公开(公告)日：2010-07-06

    申请号：US11907082

    申请日：2007-10-09

    申请人： Kyoung Lae Cho ,  Jun Jin Kong ,  Dong Hyuk Chae ,  Seung Jae Lee ,  Sung-Jae Byun ,  Dong Ku Kang

    发明人： Kyoung Lae Cho ,  Jun Jin Kong ,  Dong Hyuk Chae ,  Seung Jae Lee ,  Sung-Jae Byun ,  Dong Ku Kang

    IPC分类号： G11C11/34

    CPC分类号： G11C11/5642

    摘要： Provided are a device for reading memory data and a method using the same. The device for reading memory data comprises a memory cell which stores multi-bit information, an information detection unit which detects as much bit information as a predetermined number of bits from among multi-bit information, a source-line voltage control unit which controls a source-line voltage of the memory cell based on the detected bit information from the information detection unit, and a remaining bit information read unit which reads remaining bit information stored in the memory cell by using the controlled source-line voltage.

    摘要翻译： 提供了用于读取存储器数据的装置和使用其的方法。 用于读取存储器数据的装置包括存储多位信息的存储单元，从多位信息中检测多达位数信息作为预定位数的信息检测单元，控制位 基于来自信息检测单元的检测到的比特信息的存储器单元的源极线电压以及通过使用受控的源极线电压读取存储在存储器单元中的剩余位信息的剩余位信息读取单元。

    Device for reading memory data and method using the same
    6.
    发明申请
    Device for reading memory data and method using the same 有权
    用于读取存储器数据的装置和使用其的方法

    公开(公告)号：US20090196097A1

    公开(公告)日：2009-08-06

    申请号：US11907082

    申请日：2007-10-09

    申请人： Kyoung Lae Cho ,  Jun Jin Kong ,  Dong Hyuk Chae ,  Seung Jae Lee ,  Sung-Jae Byun ,  Dong Ku Kang

    发明人： Kyoung Lae Cho ,  Jun Jin Kong ,  Dong Hyuk Chae ,  Seung Jae Lee ,  Sung-Jae Byun ,  Dong Ku Kang

    IPC分类号： G11C16/02 ,  G11C16/06

    CPC分类号： G11C11/5642

    摘要： Provided are a device for reading memory data and a method using the same. The device for reading memory data comprises a memory cell which stores multi-bit information, an information detection unit which detects as much bit information as a predetermined number of bits from among multi-bit information, a source-line voltage control unit which controls a source-line voltage of the memory cell based on the detected bit information from the information detection unit, and a remaining bit information read unit which reads remaining bit information stored in the memory cell by using the controlled source-line voltage.

    摘要翻译： 提供了用于读取存储器数据的装置和使用其的方法。 用于读取存储器数据的装置包括存储多位信息的存储单元，从多位信息中检测多达位数信息作为预定位数的信息检测单元，控制位 基于来自信息检测单元的检测到的比特信息的存储器单元的源极线电压以及通过使用受控的源极线电压读取存储在存储器单元中的剩余位信息的剩余位信息读取单元。

    Memory system with error correction decoder architecture having reduced latency and increased throughput
    9.
    发明授权
    Memory system with error correction decoder architecture having reduced latency and increased throughput 有权
    具有纠错解码器架构的存储器系统具有降低的延迟和增加的吞吐量

    公开(公告)号：US08479085B2

    公开(公告)日：2013-07-02

    申请号：US12191458

    申请日：2008-08-14

    申请人： Nam Phil Jo ,  Jun Jin Kong ,  Chan Ho Yoon ,  Dong Hyuk Chae ,  Kyoung Lae Cho

    发明人： Nam Phil Jo ,  Jun Jin Kong ,  Chan Ho Yoon ,  Dong Hyuk Chae ,  Kyoung Lae Cho

    IPC分类号： G06F11/00

    CPC分类号： G06F11/1068 ,  G11C7/1006 ,  G11C2029/0411

    摘要： A memory system includes: a memory controller including an error correction decoder. The error correction decoder includes: a demultiplexer adapted to receive data and demultiplex the data into a first set of data and a second set of data; first and second buffer memories for storing the first and second sets of data, respectively; an error detector; an error corrector; and a multiplexer adapted to multiplex the first set of data and the second set of data and to provide the multiplexed data to the error corrector. While the error corrector corrects errors in the first set of data, the error detector detects errors in the second set of data stored in the second buffer memory.

    摘要翻译： 存储器系统包括：包括纠错解码器的存储器控​​制器。 纠错解码器包括：解复用器，适于接收数据并将数据解复用为第一组数据和第二组数据; 用于分别存储第一和第二组数据的第一和第二缓冲存储器; 误差检测器; 误差校正器 以及多路复用器，其适于多路复用第一组数据和第二组数据，并将复用的数据提供给误差校正器。 当误差校正器校正第一组数据中的错误时，误差检测器检测存储在第二缓冲存储器中的第二组数据中的错误。