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    Arbitration for memory device with commands
    1.
    发明授权
    Arbitration for memory device with commands 有权
    带指令的内存设备仲裁

    公开(公告)号：US08711652B2

    公开(公告)日：2014-04-29

    申请号：US12658911

    申请日：2010-02-17

    申请人： Young-Min Lee ,  Sung-Jae Byun ,  Han-Gu Sohn ,  Gyoo-Cheol Hwang

    发明人： Young-Min Lee ,  Sung-Jae Byun ,  Han-Gu Sohn ,  Gyoo-Cheol Hwang

    IPC分类号： G11C8/00

    CPC分类号： G11C8/16 ,  G11C7/1075 ,  G11C11/406 ,  G11C11/40603 ,  G11C11/40611

    摘要： A plurality of masters arbitrate for access to a shared memory device, such as a SDRAM (synchronous dynamic random access memory), amongst themselves using software and arbitration interfaces. The masters generate additional commands upon arbitration, such as MRS and PALL commands, for prevention of collision of commands, refresh starvation, and/or a missing pre-charge operation in the shared memory device.

    摘要翻译： 多个主机在使用软件和仲裁接口之间仲裁以访问诸如SDRAM（同步动态随机存取存储器）之类的共享存储器设备。 主机在仲裁时产生附加命令，例如MRS和PALL命令，用于防止命令冲突，刷新饥饿和/或在共享存储器设备中缺少预充电操作。

    Arbitration for memory device with commands
    3.
    发明授权
    Arbitration for memory device with commands 有权
    带指令的内存设备仲裁

    公开(公告)号：US07697362B2

    公开(公告)日：2010-04-13

    申请号：US11521655

    申请日：2006-09-15

    申请人： Young-Min Lee ,  Sung-Jae Byun ,  Han-Gu Sohn ,  Gyoo-Cheol Hwang

    发明人： Young-Min Lee ,  Sung-Jae Byun ,  Han-Gu Sohn ,  Gyoo-Cheol Hwang

    IPC分类号： G11C8/00

    CPC分类号： G11C8/16 ,  G11C7/1075 ,  G11C11/406 ,  G11C11/40603 ,  G11C11/40611

    摘要： A plurality of masters arbitrate for access to a shared memory device, such as a SDRAM (synchronous dynamic random access memory), amongst themselves using software and arbitration interfaces. The masters generate additional commands upon arbitration, such as MRS and PALL commands, for prevention of collision of commands, refresh starvation, and/or a missing pre-charge operation in the shared memory device.

    摘要翻译： 多个主机在使用软件和仲裁接口之间仲裁以访问诸如SDRAM（同步动态随机存取存储器）之类的共享存储器设备。 主机在仲裁时产生附加命令，例如MRS和PALL命令，用于防止命令冲突，刷新饥饿和/或在共享存储器设备中缺少预充电操作。

    Memory System and Memory Management Method Including the Same
    4.
    发明申请
    Memory System and Memory Management Method Including the Same 有权
    内存系统和内存管理方法包括它

    公开(公告)号：US20090210691A1

    公开(公告)日：2009-08-20

    申请号：US12430722

    申请日：2009-04-27

    申请人： Jeon-Taek Im ,  Young-Min Lee ,  Han-Gu Sohn ,  Jin-Hyoung Kwon ,  Sung-Jae Byun ,  Yun-Tae Lee ,  Gyoo-Cheol Hwang

    发明人： Jeon-Taek Im ,  Young-Min Lee ,  Han-Gu Sohn ,  Jin-Hyoung Kwon ,  Sung-Jae Byun ,  Yun-Tae Lee ,  Gyoo-Cheol Hwang

    IPC分类号： G06F15/177

    CPC分类号： G06F12/0607 ,  G06F9/4405 ,  G06F9/445 ,  G06F12/0638 ,  G06F15/177 ,  G06F2212/2022 ,  G11C8/16

    摘要： A booting method of a digital processing having a first processor and a second processor is provided. An interface between the first processor and the outside is stopped. A second processor program code is transmitted to a second memory from a first memory. A second stage loader (SSL) for the first processor is transmitted to a buffer of the second processor from the first memory. A first processor program code is transmitted to the second memory from the first memory under the control of the second processor and an interface between the first processor and the outside is resumed. The first processor program code is downloaded fast into the second memory to decrease booting time of the digital processing system.

    摘要翻译： 提供了具有第一处理器和第二处理器的数字处理的启动方法。 第一处理器和外部之间的接口被停止。 第二处理器程序代码从第一存储器发送到第二存储器。 用于第一处理器的第二级装载器（SSL）从第一存储器发送到第二处理器的缓冲器。 第一处理器程序代码在第二处理器的控制下从第一存储器发送到第二存储器，并且恢复第一处理器和外部之间的接口。 第一处理器程序代码被快速下载到第二个存储器中以减少数字处理系统的引导时间。

    Non-volatile memory devices and method thereof
    6.
    发明授权
    Non-volatile memory devices and method thereof 有权
    非易失性存储器件及其方法

    公开(公告)号：US07436704B2

    公开(公告)日：2008-10-14

    申请号：US11490129

    申请日：2006-07-21

    申请人： Won-Joo Kim ,  Sung-Jae Byun ,  Yoon-Dong Park ,  Eun-Hong Lee ,  Suk-Pil Kim ,  Jae-Woong Hyun

    发明人： Won-Joo Kim ,  Sung-Jae Byun ,  Yoon-Dong Park ,  Eun-Hong Lee ,  Suk-Pil Kim ,  Jae-Woong Hyun

    IPC分类号： G11C11/34

    CPC分类号： G11C13/0007 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C16/0416 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/72 ,  H01L27/11521 ,  H01L27/11568

    摘要： Non-volatile memory devices and a method thereof are provided. A non-volatile memory device according to an example embodiment of the present invention may include a first transistor including a source, a drain, and a control gate, a first storage node coupled to the first transistor, the first storage node configured to store information in a first manner, a first diode having a first end connected to the source of the transistor, the first diode configured to rectify a flow of current from the source of the transistor and a second storage node connected to a second end of the first diode, the second storage node configured to store information in a second manner. Another non-volatile memory device according to another example embodiment of the present invention may include a semiconductor substrate having a first conductivity type including an active region defined by a device isolating layer, a source region and a drain region formed by doping an impurity having a second conductivity type in the active region, a control gate electrode insulated from the active region, the control gate electrode extending across the active region disposed between the source region and the drain region, a first storage node layer interposed between the active region and the control gate electrode configured to store information in a first manner, a second storage node layer disposed on the source region configured to store information in a second manner and a diode interposed between the source region and the second storage node layer to rectify a flow of current to the source region. The example method may be directed to obtaining a higher storage capacity per cell area in either of the above-described example non-volatile memory devices.

    摘要翻译： 提供了非易失性存储器件及其方法。 根据本发明的示例性实施例的非易失性存储器件可以包括：第一晶体管，包括源极，漏极和控制栅极;耦合到第一晶体管的第一存储节点，第一存储节点，被配置为存储信息 以第一方式，第一二极管具有连接到晶体管的源极的第一端，第一二极管被配置为对来自晶体管的源极的电流进行整流，以及连接到第一二极管的第二端的第二存储节点 所述第二存储节点被配置为以第二方式存储信息。 根据本发明的另一示例性实施例的另一非易失性存储器件可以包括具有第一导电类型的半导体衬底，该第一导电类型包括由器件隔离层限定的有源区，源区和漏区， 有源区中的第二导电类型，与有源区绝缘的控制栅电极，跨越设置在源区和漏区之间的有源区延伸的控制栅电极，插入在有源区和控制区之间的第一存储节点层 栅电极，其被配置为以第一方式存储信息;第二存储节点层，被布置在源区域上，被配置为以第二方式存储信息;以及二极管，插入在源区域和第二存储节点层之间，以将电流流向 源区域。 示例性方法可以针对在上述任一示例非易失性存储器件中获得每个单元区域的更高的存储容量。

    Method of programming multi-level semiconductor memory device and multi-level semiconductor memory device
    8.
    发明申请
    Method of programming multi-level semiconductor memory device and multi-level semiconductor memory device 有权
    编程多电平半导体存储器件和多电平半导体存储器件的方法

    公开(公告)号：US20080159013A1

    公开(公告)日：2008-07-03

    申请号：US11978578

    申请日：2007-10-30

    申请人： Jae-woong HYUN ,  Kyoung-lae CHO ,  Kyu-charn PARK ,  Yoon-dong PARK ,  Choong-ho LEE ,  Sung-jae BYUN

    发明人： Jae-woong HYUN ,  Kyoung-lae CHO ,  Kyu-charn PARK ,  Yoon-dong PARK ,  Choong-ho LEE ,  Sung-jae BYUN

    IPC分类号： G11C7/00

    CPC分类号： G11C11/5628 ,  G11C16/10 ,  G11C2211/5642

    摘要： Provided in one example embodiment, a method of programming n bits of data to a semiconductor memory device may include outputting a first bit of data written in a memory cell from a first latch, storing the first bit of the data to a third latch, storing a second bit of the data to the first latch, outputting the second bit of the data from the first latch, storing the second bit of the data to the second latch, and writing the second bit of the data stored in the second latch to the memory cell with reference to a data storage state of the first bit of the data stored in the third latch.

    摘要翻译： 在一个示例性实施例中提供了一种将半位数据数据编程到半导体存储器件的方法可以包括从第一锁存器输出写入存储器单元中的第一位数据，将第一位数据存储到第三锁存器，存储 将数据的第二位输出到第一锁存器，从第一锁存器输出数据的第二位，将数据的第二位存储到第二锁存器，以及将存储在第二锁存器中的数据的第二位写入到 参考存储在第三锁存器中的数据的第一位的数据存储状态的存储器单元。

    Memory system and memory management method including the same
    10.
    发明授权
    Memory system and memory management method including the same 有权
    内存系统和内存管理方法包括相同

    公开(公告)号：US08209527B2

    公开(公告)日：2012-06-26

    申请号：US12430722

    申请日：2009-04-27

    申请人： Jeon-Taek Im ,  Young-Min Lee ,  Han-Gu Sohn ,  Jin-Hyoung Kwon ,  Sung-Jae Byun ,  Yun-Tae Lee ,  Gyoo-Cheol Hwang

    发明人： Jeon-Taek Im ,  Young-Min Lee ,  Han-Gu Sohn ,  Jin-Hyoung Kwon ,  Sung-Jae Byun ,  Yun-Tae Lee ,  Gyoo-Cheol Hwang

    IPC分类号： G06F15/177

    CPC分类号： G06F12/0607 ,  G06F9/4405 ,  G06F9/445 ,  G06F12/0638 ,  G06F15/177 ,  G06F2212/2022 ,  G11C8/16

    摘要： A booting method of a digital processing having a first processor and a second processor is provided. An interface between the first processor and the outside is stopped. A second processor program code is transmitted to a second memory from a first memory. A second stage loader (SSL) for the first processor is transmitted to a buffer of the second processor from the first memory. A first processor program code is transmitted to the second memory from the first memory under the control of the second processor and an interface between the first processor and the outside is resumed. The first processor program code is downloaded fast into the second memory to decrease booting time of the digital processing system.

    摘要翻译： 提供了具有第一处理器和第二处理器的数字处理的启动方法。 第一处理器和外部之间的接口被停止。 第二处理器程序代码从第一存储器发送到第二存储器。 用于第一处理器的第二级装载器（SSL）从第一存储器发送到第二处理器的缓冲器。 第一处理器程序代码在第二处理器的控制下从第一存储器发送到第二存储器，并且恢复第一处理器和外部之间的接口。 第一处理器程序代码被快速下载到第二个存储器中以减少数字处理系统的引导时间。