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    Memory system with delay locked loop (DLL) bypass control
    1.
    发明授权
    Memory system with delay locked loop (DLL) bypass control 有权
    具有延迟锁定环（DLL）旁路控制的内存系统

    公开(公告)号：US08379459B2

    公开(公告)日：2013-02-19

    申请号：US12840879

    申请日：2010-07-21

    申请人： Kyu-Hyoun Kim ,  Warren E. Maule ,  Lisa C. Gower

    发明人： Kevin C. Gower ,  Kyu-Hyoun Kim ,  Warren E. Maule

    IPC分类号： G11C7/00 ,  G11C8/00

    CPC分类号： G11C7/22 ,  G11C7/222 ,  G11C2207/2227

    摘要： A memory system with delay locked loop (DLL) bypass control including a method for accessing memory that includes receiving a memory read command at a memory device. The memory device is configured to operate in a DLL off-mode to bypass a DLL clock as input to generating a read clock. A DLL power-on command is received at the memory device and in response to receiving the DLL power-on command a DLL initialization process is performed at the memory device. The memory read command is serviced at the memory device operating in the DLL off-mode, the servicing overlapping in time with performing the DLL initialization process. The memory device is configured to operate in a DLL on-mode to utilize the DLL clock as input to generating the read clock in response to a specified period of time elapsing. The specified period of time is relative to receiving the DLL power-on command.

    摘要翻译： 具有延迟锁定环（DLL）旁路控制的存储器系统，包括用于访问存储器的方法，包括在存储器件处接收存储器读取命令。 存储器件被配置为以DLL关闭模式操作以绕过DLL时钟作为生成读取时钟的输入。 在存储器装置处接收到DLL加电命令，并且响应于接收到DLL加电命令，在存储器件执行DLL初始化处理。 存储器读取命令在以DLL关闭模式操作的存储器件处被服务，在执行DLL初始化过程时，服务与时间重叠。 存储器装置被配置为以模拟DLL操作以利用DLL时钟作为输入，以响应于经过指定的时间段来生成读取时钟。 指定的时间段相对于接收到DLL上电命令。

    MEMORY SYSTEM WITH DELAY LOCKED LOOP (DLL) BYPASS CONTROL
    2.
    发明申请
    MEMORY SYSTEM WITH DELAY LOCKED LOOP (DLL) BYPASS CONTROL 有权
    具有延迟锁定（DLL）旁路控制的存储器系统

    公开(公告)号：US20120020171A1

    公开(公告)日：2012-01-26

    申请号：US12840879

    申请日：2010-07-21

    申请人： Kevin C. Gower ,  Lisa C. Gower ,  Kyu-Hyoun Kim ,  Warren E. Maule

    发明人： Kevin C. Gower ,  Lisa C. Gower ,  Kyu-Hyoun Kim ,  Warren E. Maule

    IPC分类号： G11C8/18 ,  G11C7/00

    CPC分类号： G11C7/22 ,  G11C7/222 ,  G11C2207/2227

    摘要： A memory system with delay locked loop (DLL) bypass control including a method for accessing memory that includes receiving a memory read command at a memory device. The memory device is configured to operate in a DLL off-mode to bypass a DLL clock as input to generating a read clock. A DLL power-on command is received at the memory device and in response to receiving the DLL power-on command a DLL initialization process is performed at the memory device. The memory read command is serviced at the memory device operating in the DLL off-mode, the servicing overlapping in time with performing the DLL initialization process. The memory device is configured to operate in a DLL on-mode to utilize the DLL clock as input to generating the read clock in response to a specified period of time elapsing. The specified period of time is relative to receiving the DLL power-on command.

    摘要翻译： 具有延迟锁定环（DLL）旁路控制的存储器系统，包括用于访问存储器的方法，包括在存储器件处接收存储器读命令。 存储器件被配置为以DLL关闭模式操作以绕过DLL时钟作为生成读取时钟的输入。 在存储器装置处接收到DLL加电命令，并且响应于接收到DLL加电命令，在存储器件执行DLL初始化处理。 存储器读取命令在以DLL关闭模式操作的存储器件处被服务，在执行DLL初始化过程时，服务与时间重叠。 存储器装置被配置为以模拟DLL操作以利用DLL时钟作为输入，以响应于经过指定的时间段来生成读取时钟。 指定的时间段相对于接收DLL上电命令。

    ERROR CORRECTION AND DETECTION IN A REDUNDANT MEMORY SYSTEM
    9.
    发明申请
    ERROR CORRECTION AND DETECTION IN A REDUNDANT MEMORY SYSTEM 有权
    冗余存储系统中的错误校正和检测

    公开(公告)号：US20110320914A1

    公开(公告)日：2011-12-29

    申请号：US12822503

    申请日：2010-06-24

    申请人： Luiz C. Alves ,  Kevin C. Gower ,  Lisa C. Gower ,  Luis A. Lastras-Montano ,  Patrick J. Meaney ,  Eldee Stephens

    发明人： Luiz C. Alves ,  Kevin C. Gower ,  Lisa C. Gower ,  Luis A. Lastras-Montano ,  Patrick J. Meaney ,  Eldee Stephens

    IPC分类号： G06F11/10

    CPC分类号： G06F11/1004 ,  G06F11/108

    摘要： Error correction and detection in a redundant memory system that includes a memory controller; a plurality of memory channels in communication with the memory controller, the memory channels including a plurality of memory devices; a cyclical redundancy code (CRC) mechanism for detecting that one of the memory channels has failed, and for marking the memory channel as a failing memory channel; and an error correction code (ECC) mechanism. The ECC is configured for ignoring the marked memory channel and for detecting and correcting additional memory device failures on memory devices located on one or more of the other memory channels, thereby allowing the memory system to continue to run unimpaired in the presence of the memory channel failure.

    摘要翻译： 在包括存储器控制器的冗余存储器系统中的错误校正和检测; 与存储器控制器通信的多个存储器通道，存储器通道包括多个存储器件; 用于检测存储器通道之一的循环冗余码（CRC）机制已经失败，并用于将存储器通道标记为故障存储器通道; 和纠错码（ECC）机制。 ECC被配置为忽略标记的存储器通道并且用于检测和校正位于一个或多个其它存储器通道上的存储器设备上的附加存储器件故障，从而允许存储器系统在存在存储器通道的情况下继续运行不受损害 失败。

    HOMOGENEOUS RECOVERY IN A REDUNDANT MEMORY SYSTEM
    10.
    发明申请
    HOMOGENEOUS RECOVERY IN A REDUNDANT MEMORY SYSTEM 有权
    在冗余存储系统中均衡恢复

    公开(公告)号：US20110320869A1

    公开(公告)日：2011-12-29

    申请号：US12822964

    申请日：2010-06-24

    申请人： Kevin C. Gower ,  Lisa C. Gower ,  Luis A. Lastras-Montano ,  Patrick J. Meaney ,  Vesselina K. Papazova ,  Eldee Stephens

    发明人： Kevin C. Gower ,  Lisa C. Gower ,  Luis A. Lastras-Montano ,  Patrick J. Meaney ,  Vesselina K. Papazova ,  Eldee Stephens

    IPC分类号： G06F11/07 ,  G06F11/14

    CPC分类号： G06F11/1666 ,  G06F11/1044 ,  G06F11/108 ,  G06F11/141 ,  G06F11/1604 ,  G06F11/20 ,  G06F11/2007 ,  G06F2211/1088

    摘要： Providing homogeneous recovery in a redundant memory system that includes a memory controller, a plurality of memory channels in communication with the memory controller, an error detection code mechanism configured for detecting a failing memory channel, and an error recovery mechanism. The error recovery mechanism is configured for receiving notification of the failing memory channel, for blocking off new operations from starting on the memory channels, for completing any pending operations on the memory channels, for performing a recovery operation on the memory channels and for starting the new operations on at least a first subset of the memory channels. The memory system is capable of operating with the first subset of the memory channels.

    摘要翻译： 在包括存储器控制器，与存储器控制器通信的多个存储器通道，用于检测故障存储器通道的错误检测代码机构和错误恢复机制的冗余存储器系统中提供均匀恢复。 错误恢复机制被配置为用于接收故障存储器通道的通知，用于阻止新的操作在存储器通道上启动，以完成存储器通道上的任何未决操作，用于在存储器通道上执行恢复操作并启动 至少在存储器通道的第一子集上进行新的操作。 存储器系统能够与存储器通道的第一子集一起操作。