利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

18 条记录 (耗时 0.034 秒)

    PHASE CHANGE MEMORY DEVICES HAVING DUAL LOWER ELECTRODES AND METHODS OF FABRICATING THE SAME
    4.
    发明申请
    PHASE CHANGE MEMORY DEVICES HAVING DUAL LOWER ELECTRODES AND METHODS OF FABRICATING THE SAME 有权
    具有双下电极的相变存储器件及其制造方法

    公开(公告)号：US20100144090A1

    公开(公告)日：2010-06-10

    申请号：US12709536

    申请日：2010-02-22

    申请人： Yoon-Jong Song ,  Kyung-Chang Ryoo ,  Dong-Won Lim

    发明人： Yoon-Jong Song ,  Kyung-Chang Ryoo ,  Dong-Won Lim

    IPC分类号： H01L21/02

    CPC分类号： H01L45/144 ,  H01L27/2409 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1273 ,  H01L45/1675

    摘要： A semiconductor device includes a semiconductor substrate and a lower interlayer insulating layer disposed on the substrate. An opening passing through the lower interlayer insulating layer and exposing the substrate is included. A buried insulating pattern is disposed in the opening. First and second conductive layer patterns are sequentially stacked to surround the sidewall and bottom of the buried insulating pattern. A phase change material pattern is included, which is disposed on the lower interlayer insulating layer in contact with a top surface of the second conductive layer pattern, and spaced apart from the first conductive layer pattern. An upper interlayer insulating layer covering the lower interlayer insulating layer and the phase change material pattern is included. A conductive plug is included, which passes through the upper interlayer insulating layer and is electrically connected to the phase change material pattern. A method of fabricating the semiconductor device is also provided.

    摘要翻译： 半导体器件包括半导体衬底和设置在衬底上的下层间绝缘层。 包括通过下层间绝缘层并露出衬底的开口。 掩埋绝缘图案设置在开口中。 依次堆叠第一和第二导电层图案以围绕埋入绝缘图案的侧壁和底部。 包括相变材料图案，其设置在与第二导电层图案的顶表面接触并且与第一导电层图案间隔开的下层间绝缘层上。 包括覆盖下层间绝缘层的上层间绝缘层和相变材料图案。 包括导电塞，其穿过上层间绝缘层并电连接到相变材料图案。 还提供了制造半导体器件的方法。

    Phase change memory devices having dual lower electrodes and methods of fabricating the same
    5.
    发明授权
    Phase change memory devices having dual lower electrodes and methods of fabricating the same 有权
    具有双下电极的相变存储器件及其制造方法

    公开(公告)号：US08129214B2

    公开(公告)日：2012-03-06

    申请号：US12709536

    申请日：2010-02-22

    申请人： Yoon-Jong Song ,  Kyung-Chang Ryoo ,  Dong-Won Lim

    发明人： Yoon-Jong Song ,  Kyung-Chang Ryoo ,  Dong-Won Lim

    IPC分类号： H01L21/00 ,  H01L45/00

    CPC分类号： H01L45/144 ,  H01L27/2409 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1273 ,  H01L45/1675

    摘要： A semiconductor device includes a semiconductor substrate and a lower interlayer insulating layer disposed on the substrate. An opening passing through the lower interlayer insulating layer and exposing the substrate is included. A buried insulating pattern is disposed in the opening. First and second conductive layer patterns are sequentially stacked to surround the sidewall and bottom of the buried insulating pattern. A phase change material pattern is included, which is disposed on the lower interlayer insulating layer in contact with a top surface of the second conductive layer pattern, and spaced apart from the first conductive layer pattern. An upper interlayer insulating layer covering the lower interlayer insulating layer and the phase change material pattern is included. A conductive plug is included, which passes through the upper interlayer insulating layer and is electrically connected to the phase change material pattern. A method of fabricating the semiconductor device is also provided.

    摘要翻译： 半导体器件包括半导体衬底和设置在衬底上的下层间绝缘层。 包括通过下层间绝缘层并露出衬底的开口。 掩埋绝缘图案设置在开口中。 依次堆叠第一和第二导电层图案以围绕埋入绝缘图案的侧壁和底部。 包括相变材料图案，其设置在与第二导电层图案的顶表面接触并且与第一导电层图案间隔开的下层间绝缘层上。 包括覆盖下层间绝缘层的上层间绝缘层和相变材料图案。 包括导电塞，其穿过上层间绝缘层并电连接到相变材料图案。 还提供了制造半导体器件的方法。

    Phase change memory devices having dual lower electrodes
    6.
    发明授权
    Phase change memory devices having dual lower electrodes 有权
    具有双下电极的相变存储器件

    公开(公告)号：US07696508B2

    公开(公告)日：2010-04-13

    申请号：US11932781

    申请日：2007-10-31

    申请人： Yoon-Jong Song ,  Kyung-Chang Ryoo ,  Dong-Won Lim

    发明人： Yoon-Jong Song ,  Kyung-Chang Ryoo ,  Dong-Won Lim

    IPC分类号： H01L29/43

    CPC分类号： H01L45/144 ,  H01L27/2409 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1273 ,  H01L45/1675

    摘要： A semiconductor device includes a semiconductor substrate and a lower interlayer insulating layer disposed on the substrate. An opening passing through the lower interlayer insulating layer and exposing the substrate is included. A buried insulating pattern is disposed in the opening. First and second conductive layer patterns are sequentially stacked to surround the sidewall and bottom of the buried insulating pattern. A phase change material pattern is included, which is disposed on the lower interlayer insulating layer in contact with a top surface of the second conductive layer pattern, and spaced apart from the first conductive layer pattern. An upper interlayer insulating layer covering the lower interlayer insulating layer and the phase change material pattern is included. A conductive plug is included, which passes through the upper interlayer insulating layer and is electrically connected to the phase change material pattern. A method of fabricating the semiconductor device is also provided.

    摘要翻译： 半导体器件包括半导体衬底和设置在衬底上的下层间绝缘层。 包括通过下层间绝缘层并露出衬底的开口。 掩埋绝缘图案设置在开口中。 依次堆叠第一和第二导电层图案以围绕埋入绝缘图案的侧壁和底部。 包括相变材料图案，其设置在与第二导电层图案的顶表面接触并且与第一导电层图案间隔开的下层间绝缘层上。 包括覆盖下层间绝缘层的上层间绝缘层和相变材料图案。 包括导电塞，其穿过上层间绝缘层并电连接到相变材料图案。 还提供了制造半导体器件的方法。

    Multiple level cell phase-change memory devices having controlled resistance drift parameter, memory systems employing such devices and methods of reading memory devices
    7.
    发明申请
    Multiple level cell phase-change memory devices having controlled resistance drift parameter, memory systems employing such devices and methods of reading memory devices 有权
    具有受控电阻漂移参数的多电平单元相变存储器件，采用这种器件的存储器系统以及读取存储器件的方法

    公开(公告)号：US20080316804A1

    公开(公告)日：2008-12-25

    申请号：US12079886

    申请日：2008-03-28

    申请人： Chang-Wook Jeong ,  Dae-Hwan Kang ,  Hyeong-Jun Kim ,  Seung-Pil Ko ,  Dong-Won Lim

    发明人： Chang-Wook Jeong ,  Dae-Hwan Kang ,  Hyeong-Jun Kim ,  Seung-Pil Ko ,  Dong-Won Lim

    IPC分类号： G11C11/00

    CPC分类号： G11C11/5678 ,  G11C11/56 ,  G11C13/0004 ,  G11C13/0033 ,  G11C16/3427

    摘要： In a method of controlling resistance drift in a memory cell of a resistance-changeable material memory device, the resistance changeable material in the memory cell is treated so that a drift parameter for the memory cell is less than about 0.18, wherein a change in resistance of a memory cell over the time period is determined according to the relationship: Rdrift=Rinitial×tα; where Rdrift represents a final resistance of the memory cell following the time period, Rinitial represents the initial resistance of the memory cell following the programming operation, t represents the time period; and α represents the drift parameter.

    摘要翻译： 在电阻可变材料存储装置的存储单元中控制电阻漂移的方法中，对存储单元中的电阻变化材料进行处理，使得存储单元的漂移参数小于约0.18，其中电阻变化 根据以下关系确定该时间段内的存储单元：<？in-line-formula description =“In-line Formulas”end =“lead”？> Rdrift = Rinitialxtalpha; <？in-line-formula description = “In-Line Formulas”end =“tail”？>其中Rdrift表示在时间段之后的存储单元的最终电阻，Rinitial表示编程操作之后的存储单元的初始电阻，t表示时间段; 而alpha表示漂移参数。

    Neck of funnel and stern sealed to neck of cathode ray tube
    9.
    发明授权
    Neck of funnel and stern sealed to neck of cathode ray tube 失效
    漏斗和尾部的颈部密封到阴极射线管的颈部

    公开(公告)号：US06825605B2

    公开(公告)日：2004-11-30

    申请号：US10023798

    申请日：2001-12-21

    申请人： Jae-Young Ha ,  Kue-Hong Lee ,  Dong-Won Lim

    发明人： Jae-Young Ha ,  Kue-Hong Lee ,  Dong-Won Lim

    IPC分类号： H01J3100

    CPC分类号： H01J29/90

    摘要： A cathode ray tube includes a panel in which a phosphor layer is formed, a funnel connected to the panel, the funnel including a neck having a region for housing an electron gun and a region to which a stem is sealed, and a stem having a plurality of stem pins, each stem pin being supported by each stem mound for applying voltage to each electrode of the electron gun. The inside diameter of the stem sealing region of the neck is greater than that of the electron gun-housing region, the diameter of an inner stem pin circle formed by interior stem pins disposed on the inside of the neck is less than that of an outer stem pin circle formed by exterior stem pins disposed on the outside thereof, a horizontal length between an outer edge of the stem mound and an interior of the neck is in the range greater than or equal to 1.0 mm and less than or equal to 2.0 mm. Furthermore, the cathode ray tube includes a panel in which a phosphor layer is formed, a funnel connected to and tapered from the panel, and a neck connected to the funnel and including an electron gun housing region and a stem sealing region, to which a stem having a plurality of stem pins arranged in an annular shape and passing therethrough for introducing signal voltages from an external circuit is sealed, where D1 is 22.5±0.7 mm and D2 is in the range greater than D1 and less than or equal to 24.0 mm where the outside diameters of the electron gun-housing region and the stem sealing region are D1 and D2, respectively.

    摘要翻译： 阴极射线管包括其中形成荧光体层的面板，与面板连接的漏斗，漏斗包括具有用于容纳电子枪的区域的颈部和被密封的区域，以及具有 多个杆销，每个杆销由每个茎墩支撑，用于向电子枪的每个电极施加电压。 颈部的杆密封区域的内径大于电子枪壳体区域的内径，由设置在颈部内侧的内部针脚形成的内部针销圈的直径小于外部 由设置在其外侧的外部杆销形成的杆针圆形，茎墩的外边缘与颈部内部之间的水平长度在大于或等于1.0mm且小于或等于2.0mm的范围内 。 此外，阴极射线管包括其中形成荧光体层的面板，与面板连接并从面板成锥形的漏斗，以及连接到漏斗的颈部，并且包括电子枪容纳区域和杆密封区域，其中 具有多个设置成环状并通过其从外部电路引入信号电压的杆销的杆被密封，其中D1为22.5±0.7mm，D2在大于D1且小于或等于24.0mm的范围内 其中电子枪壳体区域和杆密封区域的外径分别为D1和D2。

    Phase change memory device and method of fabricating the same
    10.
    发明申请
    Phase change memory device and method of fabricating the same 有权
    相变存储器件及其制造方法

    公开(公告)号：US20090242866A1

    公开(公告)日：2009-10-01

    申请号：US12382781

    申请日：2009-03-24

    申请人： Seung-Pil Ko ,  Jae-Hee Oh ,  Jung-Hoon Park ,  Yoon-Jong Song ,  Jae-Hyun Park ,  Dong-Won Lim

    发明人： Seung-Pil Ko ,  Jae-Hee Oh ,  Jung-Hoon Park ,  Yoon-Jong Song ,  Jae-Hyun Park ,  Dong-Won Lim

    IPC分类号： H01L47/00 ,  H01L21/00

    CPC分类号： H01L45/144 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1683

    摘要： A semiconductor device includes an insulating layer on a substrate, a first electrode in the insulating layer having a first upper surface and a second upper surface, a second electrode in the insulating layer spaced apart from the first electrode by a first distance and having a third upper surface and a fourth upper surface, the third upper surface being disposed at a substantially same level as the first upper surface, and the fourth upper surface being disposed at a substantially same level as the second upper surface, a first phase change material pattern covering a part of the first upper surface of the first electrode, and a second phase change material pattern covering a part of the third upper surface of the second electrode, wherein an interface region between the second phase change pattern and the second electrode is spaced apart from an interface region between the first phase change pattern and the first electrode by a second distance greater than the first distance.

    摘要翻译： 半导体器件在衬底上包括绝缘层，绝缘层中的第一电极具有第一上表面和第二上表面，绝缘层中的第二电极与第一电极隔开第一距离，并具有第三距离 上表面和第四上表面，所述第三上表面设置在与所述第一上表面基本相同的高度，所述第四上表面设置在与所述第二上表面基本相同的水平面上，所述第一相变材料图案覆盖 第一电极的第一上表面的一部分和覆盖第二电极的第三上表面的一部分的第二相变材料图案，其中第二相变图案和第二电极之间的界面区域与 所述第一相变图案和所述第一电极之间的界面区域大于所述第一距离的第二距离。