Phase-changeable memory devices having reduced susceptibility to thermal interference
    3.
    发明授权
    Phase-changeable memory devices having reduced susceptibility to thermal interference 有权
    相变型存储器件具有降低的对热干扰的敏感性

    公开(公告)号:US07977662B2

    公开(公告)日:2011-07-12

    申请号:US12265262

    申请日:2008-11-05

    IPC分类号: H01L29/06 H01L47/00

    摘要: A non-volatile memory array includes an array of phase-changeable memory elements that are electrically insulated from each other by at least a first electrically insulating region extending between the array of phase-changeable memory elements. The first electrically insulating region includes a plurality of voids therein. Each of these voids extends between a corresponding pair of phase-changeable memory cells in the non-volatile memory array and, collectively, the voids form an array of voids in the first electrically insulating region.

    摘要翻译: 非易失性存储器阵列包括相变存储元件的阵列,它们通过在可相变存储元件阵列之间延伸的至少第一电绝缘区域彼此电绝缘。 第一电绝缘区域中包括多个空隙。 这些空隙中的每一个在非易失性存储器阵列中相应的一对相位可变存储单元之间延伸,并且总体上空隙在第一电绝缘区域中形成一组空隙。

    PHASE CHANGE MEMORY DEVICES HAVING DUAL LOWER ELECTRODES AND METHODS OF FABRICATING THE SAME
    4.
    发明申请
    PHASE CHANGE MEMORY DEVICES HAVING DUAL LOWER ELECTRODES AND METHODS OF FABRICATING THE SAME 有权
    具有双下电极的相变存储器件及其制造方法

    公开(公告)号:US20100144090A1

    公开(公告)日:2010-06-10

    申请号:US12709536

    申请日:2010-02-22

    IPC分类号: H01L21/02

    摘要: A semiconductor device includes a semiconductor substrate and a lower interlayer insulating layer disposed on the substrate. An opening passing through the lower interlayer insulating layer and exposing the substrate is included. A buried insulating pattern is disposed in the opening. First and second conductive layer patterns are sequentially stacked to surround the sidewall and bottom of the buried insulating pattern. A phase change material pattern is included, which is disposed on the lower interlayer insulating layer in contact with a top surface of the second conductive layer pattern, and spaced apart from the first conductive layer pattern. An upper interlayer insulating layer covering the lower interlayer insulating layer and the phase change material pattern is included. A conductive plug is included, which passes through the upper interlayer insulating layer and is electrically connected to the phase change material pattern. A method of fabricating the semiconductor device is also provided.

    摘要翻译: 半导体器件包括半导体衬底和设置在衬底上的下层间绝缘层。 包括通过下层间绝缘层并露出衬底的开口。 掩埋绝缘图案设置在开口中。 依次堆叠第一和第二导电层图案以围绕埋入绝缘图案的侧壁和底部。 包括相变材料图案,其设置在与第二导电层图案的顶表面接触并且与第一导电层图案间隔开的下层间绝缘层上。 包括覆盖下层间绝缘层的上层间绝缘层和相变材料图案。 包括导电塞,其穿过上层间绝缘层并电连接到相变材料图案。 还提供了制造半导体器件的方法。

    Phase-Changeable Fuse Elements and Memory Devices Containing Phase-Changeable Fuse Elements and Memory Cells Therein
    7.
    发明申请
    Phase-Changeable Fuse Elements and Memory Devices Containing Phase-Changeable Fuse Elements and Memory Cells Therein 审中-公开
    相变保险丝元件和包含相变保险丝元件和存储器单元的存储器件

    公开(公告)号:US20100072453A1

    公开(公告)日:2010-03-25

    申请号:US12492275

    申请日:2009-06-26

    IPC分类号: H01L45/00

    摘要: Non-volatile memory devices include an array of phase-changeable memory cells, which have first phase-changeable material patterns therein, and at least one phase-changeable fuse element. This phase-changeable fuse element includes a second phase-changeable material pattern therein with a higher crystallization temperature relative to the first phase-changeable material patterns in the array of phase-changeable memory cells. This higher crystallization temperature may be greater than about 300° C. According to additional embodiments of the present invention, the at least one phase-changeable fuse element includes a composite of the second phase-changeable material pattern and a third phase-changeable material pattern, which is formed of the same material at the first phase-changeable material patterns.

    摘要翻译: 非易失性存储器件包括其中具有第一相变材料图案的相变存储器单元阵列和至少一个相变型熔丝元件。 该可相变熔丝元件包括其中相对于可相变存储器单元阵列中的第一可相变材料图案具有较高结晶温度的第二相变材料图案。 该较高的结晶温度可以大于约300℃。根据本发明的另外的实施方案,至少一个可相变熔丝元件包括第二相变材料图案和第三可相变材料图案的复合材料 ,其由第一相变材料图案上的相同材料形成。