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    Semiconductor fabrication apparatuses to perform semiconductor etching and deposition processes and methods of forming semiconductor device using the same
    2.
    发明授权
    Semiconductor fabrication apparatuses to perform semiconductor etching and deposition processes and methods of forming semiconductor device using the same 有权
    用于执行半导体蚀刻和沉积工艺的半导体制造装置以及使用其形成半导体器件的方法

    公开(公告)号：US08197637B2

    公开(公告)日：2012-06-12

    申请号：US12033266

    申请日：2008-02-19

    申请人： Kyung-Woo Lee ,  Jin-Sung Kim ,  Joo-Byoung Yoon ,  Yeong-Cheol Lee ,  Sang-Jun Park ,  Hee-Kyeong Jeon

    发明人： Kyung-Woo Lee ,  Jin-Sung Kim ,  Joo-Byoung Yoon ,  Yeong-Cheol Lee ,  Sang-Jun Park ,  Hee-Kyeong Jeon

    IPC分类号： H01L21/33

    CPC分类号： H01L21/02087 ,  H01J37/32009 ,  H01J37/32587 ,  H01L21/02057 ,  H01L21/0209

    摘要： A semiconductor fabrication apparatus and a method of fabricating a semiconductor device using the same performs semiconductor etching and deposition processes at an edge of a semiconductor substrate after disposing the semiconductor substrate at a predetermined place in the semiconductor fabrication apparatus. The semiconductor fabrication apparatus has lower, middle and upper electrodes sequentially stacked. The semiconductor substrate is disposed on the middle electrode. Semiconductor etching and deposition processes are performed on the semiconductor substrate in the semiconductor fabrication apparatus. The semiconductor fabrication apparatus forms electrical fields along an edge of the middle electrode during performance of the semiconductor etching and deposition processes.

    摘要翻译： 半导体制造装置和使用该半导体制造装置的半导体装置的制造方法在将半导体基板设置在半导体制造装置中的预定位置之后，在半导体基板的边缘进行半导体蚀刻和沉积处理。 半导体制造装置具有顺序堆叠的下部，中间和上部电极。 半导体衬底设置在中间电极上。 在半导体制造装置中的半导体衬底上进行半导体蚀刻和沉积处理。 半导体制造装置在半导体蚀刻和沉积工艺的执行期间沿着中间电极的边缘形成电场。

    Methods of manufacturing a semiconductor device
    5.
    发明授权
    Methods of manufacturing a semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US07375003B2

    公开(公告)日：2008-05-20

    申请号：US11240048

    申请日：2005-09-30

    申请人： Joo-Byoung Yoon ,  Jin-Sung Kim ,  Kyung-Woo Lee ,  Yeong-Cheol Lee ,  Sang-Jun Park ,  Hwan-Shik Park

    发明人： Joo-Byoung Yoon ,  Jin-Sung Kim ,  Kyung-Woo Lee ,  Yeong-Cheol Lee ,  Sang-Jun Park ,  Hwan-Shik Park

    IPC分类号： H01L21/20

    CPC分类号： H01L21/76897 ,  H01L27/10852 ,  H01L28/91

    摘要： In a method of manufacturing a semiconductor device including a capacitor, a first mold layer is formed on a semiconductor substrate. The first mold layer is partially etched to form a first mold layer pattern including an opening for a capacitor. A first lower electrode layer is formed on the first mold layer pattern. A second lower electrode layer including a plurality of first pores is formed on the first lower electrode layer and in the opening. Upper portions of the first lower electrode layer and the second lower electrode layer are removed to form a first lower electrode and a second lower electrode in the opening. A dielectric layer and an upper electrode are successively formed on the first lower electrode and the second lower electrode. Therefore, a capacitor having an enhanced capacitance may be obtained.

    摘要翻译： 在制造包括电容器的半导体器件的方法中，在半导体衬底上形成第一模制层。 部分蚀刻第一模具层以形成包括用于电容器的开口的第一模具层图案。 第一下电极层形成在第一模层图案上。 包括多个第一孔的第二下电极层形成在第一下电极层和开口中。 去除第一下电极层和第二下电极层的上部，以在开口中形成第一下电极和第二下电极。 电介质层和上电极依次形成在第一下电极和第二下电极上。 因此，可以获得具有增大的电容的电容器。

    Methods of manufacturing a semiconductor device
    7.
    发明申请
    Methods of manufacturing a semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US20060073691A1

    公开(公告)日：2006-04-06

    申请号：US11240048

    申请日：2005-09-30

    申请人： Joo-Byoung Yoon ,  Jin-Sung Kim ,  Kyung-Woo Lee ,  Yeong-Cheol Lee ,  Sang-Jun Park ,  Hwan-Shik Park

    发明人： Joo-Byoung Yoon ,  Jin-Sung Kim ,  Kyung-Woo Lee ,  Yeong-Cheol Lee ,  Sang-Jun Park ,  Hwan-Shik Park

    IPC分类号： H01L21/44

    CPC分类号： H01L21/76897 ,  H01L27/10852 ,  H01L28/91

    摘要： In a method of manufacturing a semiconductor device including a capacitor, a first mold layer is formed on a semiconductor substrate. The first mold layer is partially etched to form a first mold layer pattern including an opening for a capacitor. A first lower electrode layer is formed on the first mold layer pattern. A second lower electrode layer including a plurality of first pores is formed on the first lower electrode layer and in the opening. Upper portions of the first lower electrode layer and the second lower electrode layer are removed to form a first lower electrode and a second lower electrode in the opening. A dielectric layer and an upper electrode are successively formed on the first lower electrode and the second lower electrode. Therefore, a capacitor having an enhanced capacitance may be obtained.

    摘要翻译： 在制造包括电容器的半导体器件的方法中，在半导体衬底上形成第一模制层。 部分蚀刻第一模具层以形成包括用于电容器的开口的第一模具层图案。 第一下电极层形成在第一模层图案上。 包括多个第一孔的第二下电极层形成在第一下电极层和开口中。 去除第一下电极层和第二下电极层的上部，以在开口中形成第一下电极和第二下电极。 电介质层和上电极依次形成在第一下电极和第二下电极上。 因此，可以获得具有增大的电容的电容器。

    Methods of fabricating gate insulating layers in gate trenches and methods of fabricating semiconductor devices including the same
    8.
    发明授权
    Methods of fabricating gate insulating layers in gate trenches and methods of fabricating semiconductor devices including the same 有权
    在栅极沟槽中制造栅极绝缘层的方法以及制造包括其的半导体器件的方法

    公开(公告)号：US09312124B2

    公开(公告)日：2016-04-12

    申请号：US13605463

    申请日：2012-09-06

    申请人： Tai-Su Park ,  Gun-Joong Lee ,  Young-Dong Lee ,  Sang-Chul Han ,  Joo-Byoung Yoon

    发明人： Tai-Su Park ,  Gun-Joong Lee ,  Young-Dong Lee ,  Sang-Chul Han ,  Joo-Byoung Yoon

    IPC分类号： H01L21/02 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

    CPC分类号： H01L21/02238 ,  H01L21/02252 ,  H01L21/02255 ,  H01L29/42356 ,  H01L29/4966 ,  H01L29/78

    摘要： A method of fabricating a semiconductor device may include: forming a field region defining an active region in a substrate; forming a gate trench in which the active and field regions are partially exposed; forming a gate insulating layer on a surface of the active region; conformally forming a gate barrier layer including metal on the gate insulating layer and partially exposed field region; forming a gate electrode layer including metal on the gate barrier layer; and/or forming a gate capping layer. Forming the gate insulating layer may include forming a first gate oxide layer by primarily oxidizing the active region's surface, and forming a second gate oxide layer between the active region's surface and the first gate oxide layer by secondarily oxidizing the active region's surface. The gate capping layer may be in contact with the gate insulating layer, gate barrier layer, and/or gate electrode layer.

    摘要翻译： 制造半导体器件的方法可以包括：在衬底中形成限定有源区的场区; 形成栅极沟槽，其中所述有源场区域和所述场区域部分地暴露; 在有源区的表面上形成栅极绝缘层; 在栅极绝缘层和部分曝光的场区域上保形地形成包括金属的栅极阻挡层; 在栅极阻挡层上形成包含金属的栅电极层; 和/或形成栅极覆盖层。 形成栅极绝缘层可以包括通过主要氧化有源区的表面形成第一栅极氧化层，并且通过二次氧化活性区的表面在有源区的表面和第一栅极氧化物层之间形成第二栅极氧化物层。 栅极覆盖层可以与栅极绝缘层，栅极势垒层和/或栅极电极层接触。