公开(公告)号：US20100203700A1

公开(公告)日：2010-08-12

申请号：US12686638

申请日：2010-01-13

申请人： Kyungmun Byun ,  Deok-Young Jung ,  Ju-Seon Goo ,  Eunkee Hong

发明人： Kyungmun Byun ,  Deok-Young Jung ,  Ju-Seon Goo ,  Eunkee Hong

IPC分类号： H01L21/762

CPC分类号： H01L21/76224 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76837

摘要： A method of forming a semiconductor device includes preparing a substrate having a recessed area. A silicon oxide layer is formed at the recessed area. A catalytic nitridation treatment is performed for an upper portion of the silicon oxide layer to form a nitridation reactant on the upper portion of the silicon oxide layer. A dielectric layer is formed on the silicon oxide layer where the nitridation reactant is formed. The dielectric layer is annealed. According to the foregoing method, recession of the dielectric layer is prevented to fabricate a high-quality semiconductor device.

摘要翻译： 形成半导体器件的方法包括制备具有凹陷区域的衬底。 在凹陷区域形成氧化硅层。 对氧化硅层的上部进行催化氮化处理，以在氧化硅层的上部形成氮化反应物。 在形成氮化反应物的氧化硅层上形成介电层。 电介质层退火。 根据上述方法，防止了电介质层的凹陷以制造高质量的半导体器件。

公开(公告)号：US20060089008A1

公开(公告)日：2006-04-27

申请号：US11259408

申请日：2005-10-26

申请人： Eunkee Hong ,  Ju-Seon Goo ,  Kyu-Tae Na ,  Sang-Ho Rha

发明人： Eunkee Hong ,  Ju-Seon Goo ,  Kyu-Tae Na ,  Sang-Ho Rha

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/76232 ,  H01L21/02164 ,  H01L21/02222 ,  H01L21/02282 ,  H01L21/02337 ,  H01L21/3125 ,  H01L21/316

摘要： Methods of manufacturing silicon oxide layers for semiconductor devices are provided in which a substrate having a recess is coated with a spin-on-glass film so that the recess is filled with the spin-on-glass film. A main thermal treatment is performed on the spin-on-glass film at about 600 to about 1,000° C. at about 1 ATM to about 50 ATM so that the spin-on-glass film is converted into a relatively dense silicon oxide layer.

摘要翻译： 提供了制造用于半导体器件的氧化硅层的方法，其中具有凹陷的衬底涂覆有旋涂玻璃膜，使得凹部填充有旋涂玻璃膜。 在旋转玻璃膜上进行主要的热处理，在约1 00至约1000℃，约1个ATM至约50个ATM处进行，以使旋涂玻璃膜转化成相对致密的氧化硅层。

公开(公告)号：US08043914B2

公开(公告)日：2011-10-25

申请号：US12629920

申请日：2009-12-03

申请人： Jong-wan Choi ,  Yong-soon Choi ,  Bo-young Lee ,  Eunkee Hong ,  Eun-kyung Baek ,  Ju-seon Goo

发明人： Jong-wan Choi ,  Yong-soon Choi ,  Bo-young Lee ,  Eunkee Hong ,  Eun-kyung Baek ,  Ju-seon Goo

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/11524

摘要： Provided are methods of fabricating flash memory devices that may prevent a short circuit from occurring between cell gate lines. Methods of fabricating such flash memory devices may include forming gate lines including a series of multiple cell gate lines and multiple selection gate lines. Each gate line may include a stacked structure of a tunnel insulating layer, a floating gate, a gate insulating layer, and/or a polysilicon layer operable to be a control gate, all formed on a semiconductor substrate. Methods may include forming a first insulating layer that selectively fills gaps between the cell gate lines from the bottom up and between adjacent ones of the cell gate lines and the selection gate lines, and does not fill a space located on outer sides of the selection gate lines that are opposite the plurality of cell gate lines. A spacer may be formed on the outer sides of the selection gate lines that are opposite to the cell gate lines, after forming the first insulating layer. A second insulating layer may be formed in a space where the spacer is formed.

摘要翻译： 提供了制造闪存器件的方法，其可以防止在单元栅极线之间发生短路。 制造这种闪存器件的方法可以包括形成包括一系列多单元栅极线和多个选择栅极线的栅极线。 每个栅极线可以包括全部形成在半导体衬底上的隧道绝缘层，浮动栅极，栅极绝缘层和/或可操作为控制栅极的多晶硅层的堆叠结构。 方法可以包括形成第一绝缘层，其选择性地从底部向上和相邻的单元栅极线和选择栅极线之间填充单元栅极线之间的间隙，并且不填充位于选择栅极的外侧的空间 与多个单元栅极线相对的线。 在形成第一绝缘层之后，可以在选择栅极线的与单元栅极线相对的外侧上形成间隔物。 可以在形成间隔物的空间中形成第二绝缘层。

公开(公告)号：US20110256708A1

公开(公告)日：2011-10-20

申请号：US13085631

申请日：2011-04-13

申请人： Jong-wan Choi ,  Wan-sik Hwang ,  Gil-heyun Choi ,  Eunkee Hong ,  Ju-seon Goo ,  Bo-young Lee

发明人： Jong-wan Choi ,  Wan-sik Hwang ,  Gil-heyun Choi ,  Eunkee Hong ,  Ju-seon Goo ,  Bo-young Lee

IPC分类号： H01L21/321 ,  H01L21/283

CPC分类号： H01L21/3105 ,  H01L21/76826 ,  H01L27/11521

摘要： A method of manufacturing a flash memory device includes: forming a dielectric layer on an active region of a substrate having an isolation region and the active region; forming a floating gate on the dielectric layer; forming an isolation layer in the isolation region; forming a nitride layer including a first nitride layer portion formed on an exposed surface of the floating gate and a second nitride layer portion formed on an exposed surface of the isolation layer; selectively removing nitrogen atoms from the second nitride layer portion of the nitride layer; forming an inter-gate dielectric layer on both the first nitride layer portion and the isolation layer; and forming a control gate on the inter-gate dielectric layer.

摘要翻译： 制造闪速存储器件的方法包括：在具有隔离区域和有源区域的衬底的有源区上形成电介质层; 在介电层上形成浮栅; 在隔离区中形成隔离层; 形成包括形成在所述浮置栅极的暴露表面上的第一氮化物层部分和形成在所述隔离层的暴露表面上的第二氮化物层部分的氮化物层; 从氮化物层的第二氮化物层部分选择性地除去氮原子; 在所述第一氮化物层部分和所述隔离层上形成栅极间电介质层; 以及在所述栅极间电介质层上形成控制栅极。

公开(公告)号：US20100240194A1

公开(公告)日：2010-09-23

申请号：US12659841

申请日：2010-03-23

申请人： DeokYoung Jung ,  Ju-Seon Goo ,  Kyung-Mun Byun ,  Eunkee Hong ,  Jun-Won Lee

发明人： DeokYoung Jung ,  Ju-Seon Goo ,  Kyung-Mun Byun ,  Eunkee Hong ,  Jun-Won Lee

IPC分类号： H01L21/762

CPC分类号： H01L21/76224 ,  H01L21/76232

摘要： A method of fabricating a semiconductor device, the method including sequentially forming a pad oxide layer and a nitride layer on a substrate; etching the nitride layer, the pad oxide layer, and the substrate to form a trench; forming a sidewall oxide layer on a sidewall and a bottom of the trench; forming a oxide layer liner including nitrogen on the sidewall oxide layer; and forming a gap fill layer on the oxide layer liner

摘要翻译： 一种制造半导体器件的方法，所述方法包括在衬底上依次形成衬垫氧化物层和氮化物层; 蚀刻氮化物层，衬垫氧化物层和衬底以形成沟槽; 在沟槽的侧壁和底部上形成侧壁氧化物层; 在所述侧壁氧化物层上形成包括氮的氧化物层衬垫; 并在氧化层衬垫上形成间隙填充层

公开(公告)号：US20050277265A1

公开(公告)日：2005-12-15

申请号：US11149307

申请日：2005-06-09

申请人： Yong-Won Cha ,  Kyu-Tae Na ,  Yong-Soon Choi ,  Eunkee Hong ,  Ju-Seon Goo

发明人： Yong-Won Cha ,  Kyu-Tae Na ,  Yong-Soon Choi ,  Eunkee Hong ,  Ju-Seon Goo

IPC分类号： H01L21/76 ,  H01L21/762

CPC分类号： H01L21/76224

摘要： A method of forming a trench isolation layer can include forming an isolation layer in a trench using High Density Plasma Chemical Vapor Deposition (HDPCVD) with a carrier gas comprising hydrogen. Other methods are disclosed.

摘要翻译： 形成沟槽隔离层的方法可以包括使用具有包含氢的载气的高密度等离子体化学气相沉积（HDPCVD）在沟槽中形成隔离层。 公开了其他方法。

公开(公告)号：US07332409B2

公开(公告)日：2008-02-19

申请号：US11149307

申请日：2005-06-09

申请人： Yong-Won Cha ,  Kyu-Tae Na ,  Yong-Soon Choi ,  Eunkee Hong ,  Ju-Seon Goo

发明人： Yong-Won Cha ,  Kyu-Tae Na ,  Yong-Soon Choi ,  Eunkee Hong ,  Ju-Seon Goo

IPC分类号： H01L21/76

CPC分类号： H01L21/76224

摘要： A method of forming a trench isolation layer can include forming an isolation layer in a trench using High Density Plasma Chemical Vapor Deposition (HDPCVD) with a carrier gas comprising hydrogen. Other methods are disclosed.

摘要翻译： 形成沟槽隔离层的方法可以包括使用具有包含氢的载气的高密度等离子体化学气相沉积（HDPCVD）在沟槽中形成隔离层。 公开了其他方法。

公开(公告)号：US08492223B2

公开(公告)日：2013-07-23

申请号：US13085631

申请日：2011-04-13

申请人： Jong-wan Choi ,  Wan-sik Hwang ,  Gil-heyun Choi ,  Eunkee Hong ,  Ju-seon Goo ,  Bo-young Lee

发明人： Jong-wan Choi ,  Wan-sik Hwang ,  Gil-heyun Choi ,  Eunkee Hong ,  Ju-seon Goo ,  Bo-young Lee

IPC分类号： H01L21/321

CPC分类号： H01L21/3105 ,  H01L21/76826 ,  H01L27/11521

摘要： A method of manufacturing a flash memory device includes: forming a dielectric layer on an active region of a substrate having an isolation region and the active region; forming a floating gate on the dielectric layer; forming an isolation layer in the isolation region; forming a nitride layer including a first nitride layer portion formed on an exposed surface of the floating gate and a second nitride layer portion formed on an exposed surface of the isolation layer; selectively removing nitrogen atoms from the second nitride layer portion of the nitride layer; forming an inter-gate dielectric layer on both the first nitride layer portion and the isolation layer; and forming a control gate on the inter-gate dielectric layer.

摘要翻译： 制造闪速存储器件的方法包括：在具有隔离区域和有源区域的衬底的有源区上形成电介质层; 在介电层上形成浮栅; 在隔离区中形成隔离层; 形成包括形成在所述浮置栅极的暴露表面上的第一氮化物层部分和形成在所述隔离层的暴露表面上的第二氮化物层部分的氮化物层; 从氮化物层的第二氮化物层部分选择性地除去氮原子; 在所述第一氮化物层部分和所述隔离层上形成栅极间电介质层; 以及在所述栅极间电介质层上形成控制栅极。

公开(公告)号：US20100167490A1

公开(公告)日：2010-07-01

申请号：US12629920

申请日：2009-12-03

申请人： Jong-wan Choi ,  Yong-soon Choi ,  Bo-young Lee ,  Eunkee Hong ,  Eun-kyung Baek ,  Ju-seon Goo

发明人： Jong-wan Choi ,  Yong-soon Choi ,  Bo-young Lee ,  Eunkee Hong ,  Eun-kyung Baek ,  Ju-seon Goo

IPC分类号： H01L21/762

CPC分类号： H01L27/11521 ,  H01L27/11524

摘要： Provided are methods of fabricating flash memory devices that may prevent a short circuit from occurring between cell gate lines. Methods of fabricating such flash memory devices may include forming gate lines including a series of multiple cell gate lines and multiple selection gate lines. Each gate line may include a stacked structure of a tunnel insulating layer, a floating gate, a gate insulating layer, and/or a polysilicon layer operable to be a control gate, all formed on a semiconductor substrate. Methods may include forming a first insulating layer that selectively fills gaps between the cell gate lines from the bottom up and between adjacent ones of the cell gate lines and the selection gate lines, and does not fill a space located on outer sides of the selection gate lines that are opposite the plurality of cell gate lines. A spacer may be formed on the outer sides of the selection gate lines that are opposite to the cell gate lines, after forming the first insulating layer. A second insulating layer may be formed in a space where the spacer is formed.

摘要翻译： 提供了制造闪存器件的方法，其可以防止在单元栅极线之间发生短路。 制造这种闪存器件的方法可以包括形成包括一系列多单元栅极线和多个选择栅极线的栅极线。 每个栅极线可以包括全部形成在半导体衬底上的隧道绝缘层，浮动栅极，栅极绝缘层和/或可操作为控制栅极的多晶硅层的堆叠结构。 方法可以包括形成第一绝缘层，其选择性地从底部向上和相邻的单元栅极线和选择栅极线之间填充单元栅极线之间的间隙，并且不填充位于选择栅极的外侧的空间 与多个单元栅极线相对的线。 在形成第一绝缘层之后，可以在选择栅极线的与单元栅极线相对的外侧上形成间隔物。 可以在形成间隔物的空间中形成第二绝缘层。

公开(公告)号：US20090012221A1

公开(公告)日：2009-01-08

申请号：US12194313

申请日：2008-08-19

申请人： Eunkee Hong ,  Kyu-Tae Na ,  Ju-Seon Goo ,  Hong-Gun Kim

发明人： Eunkee Hong ,  Kyu-Tae Na ,  Ju-Seon Goo ,  Hong-Gun Kim

IPC分类号： C08K5/06 ,  C08L83/08

CPC分类号： H01L21/3125 ,  H01L21/02164 ,  H01L21/02222 ,  H01L21/02282 ,  H01L21/02337 ,  H01L21/316 ,  H01L21/31695 ,  H01L21/76232 ,  H01L21/76837

摘要： A film is formed on a substrate including conductive patterns or trenches using a composition that included a solvent and perhydro-polysilazane having a weight average molecular weight of about 1,800 to 3,000 and a molecular weight distribution of more than about 2.2 to about 3.0. The film is changed into a silicon oxide film, and then an opening is formed through the silicon oxide film. A contact is formed in the opening by filling the opening with conductive material. The silicon oxide film of perhydro-polysilazane having low molecular weight becomes dense and uniform.

摘要翻译： 使用包含重量平均分子量约1,800至3,000且分子量分布大于约2.2至约3.0的溶剂和全氢化聚硅氮烷的组合物在包括导电图案或沟槽的基材上形成膜。 将膜变成氧化硅膜，然后通过氧化硅膜形成开口。 通过用导电材料填充开口在开口中形成接触。 具有低分子量的全氢聚硅氮烷的氧化硅膜变得致密且均匀。