公开(公告)号：US20110256708A1

公开(公告)日：2011-10-20

申请号：US13085631

申请日：2011-04-13

申请人： Jong-wan Choi ,  Wan-sik Hwang ,  Gil-heyun Choi ,  Eunkee Hong ,  Ju-seon Goo ,  Bo-young Lee

发明人： Jong-wan Choi ,  Wan-sik Hwang ,  Gil-heyun Choi ,  Eunkee Hong ,  Ju-seon Goo ,  Bo-young Lee

IPC分类号： H01L21/321 ,  H01L21/283

CPC分类号： H01L21/3105 ,  H01L21/76826 ,  H01L27/11521

摘要： A method of manufacturing a flash memory device includes: forming a dielectric layer on an active region of a substrate having an isolation region and the active region; forming a floating gate on the dielectric layer; forming an isolation layer in the isolation region; forming a nitride layer including a first nitride layer portion formed on an exposed surface of the floating gate and a second nitride layer portion formed on an exposed surface of the isolation layer; selectively removing nitrogen atoms from the second nitride layer portion of the nitride layer; forming an inter-gate dielectric layer on both the first nitride layer portion and the isolation layer; and forming a control gate on the inter-gate dielectric layer.

摘要翻译： 制造闪速存储器件的方法包括：在具有隔离区域和有源区域的衬底的有源区上形成电介质层; 在介电层上形成浮栅; 在隔离区中形成隔离层; 形成包括形成在所述浮置栅极的暴露表面上的第一氮化物层部分和形成在所述隔离层的暴露表面上的第二氮化物层部分的氮化物层; 从氮化物层的第二氮化物层部分选择性地除去氮原子; 在所述第一氮化物层部分和所述隔离层上形成栅极间电介质层; 以及在所述栅极间电介质层上形成控制栅极。

公开(公告)号：US08492223B2

公开(公告)日：2013-07-23

申请号：US13085631

申请日：2011-04-13

申请人： Jong-wan Choi ,  Wan-sik Hwang ,  Gil-heyun Choi ,  Eunkee Hong ,  Ju-seon Goo ,  Bo-young Lee

发明人： Jong-wan Choi ,  Wan-sik Hwang ,  Gil-heyun Choi ,  Eunkee Hong ,  Ju-seon Goo ,  Bo-young Lee

IPC分类号： H01L21/321

CPC分类号： H01L21/3105 ,  H01L21/76826 ,  H01L27/11521

摘要： A method of manufacturing a flash memory device includes: forming a dielectric layer on an active region of a substrate having an isolation region and the active region; forming a floating gate on the dielectric layer; forming an isolation layer in the isolation region; forming a nitride layer including a first nitride layer portion formed on an exposed surface of the floating gate and a second nitride layer portion formed on an exposed surface of the isolation layer; selectively removing nitrogen atoms from the second nitride layer portion of the nitride layer; forming an inter-gate dielectric layer on both the first nitride layer portion and the isolation layer; and forming a control gate on the inter-gate dielectric layer.

摘要翻译： 制造闪速存储器件的方法包括：在具有隔离区域和有源区域的衬底的有源区上形成电介质层; 在介电层上形成浮栅; 在隔离区中形成隔离层; 形成包括形成在所述浮置栅极的暴露表面上的第一氮化物层部分和形成在所述隔离层的暴露表面上的第二氮化物层部分的氮化物层; 从氮化物层的第二氮化物层部分选择性地除去氮原子; 在所述第一氮化物层部分和所述隔离层上形成栅极间电介质层; 以及在所述栅极间电介质层上形成控制栅极。

公开(公告)号：US08043914B2

公开(公告)日：2011-10-25

申请号：US12629920

申请日：2009-12-03

申请人： Jong-wan Choi ,  Yong-soon Choi ,  Bo-young Lee ,  Eunkee Hong ,  Eun-kyung Baek ,  Ju-seon Goo

发明人： Jong-wan Choi ,  Yong-soon Choi ,  Bo-young Lee ,  Eunkee Hong ,  Eun-kyung Baek ,  Ju-seon Goo

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/11524

摘要： Provided are methods of fabricating flash memory devices that may prevent a short circuit from occurring between cell gate lines. Methods of fabricating such flash memory devices may include forming gate lines including a series of multiple cell gate lines and multiple selection gate lines. Each gate line may include a stacked structure of a tunnel insulating layer, a floating gate, a gate insulating layer, and/or a polysilicon layer operable to be a control gate, all formed on a semiconductor substrate. Methods may include forming a first insulating layer that selectively fills gaps between the cell gate lines from the bottom up and between adjacent ones of the cell gate lines and the selection gate lines, and does not fill a space located on outer sides of the selection gate lines that are opposite the plurality of cell gate lines. A spacer may be formed on the outer sides of the selection gate lines that are opposite to the cell gate lines, after forming the first insulating layer. A second insulating layer may be formed in a space where the spacer is formed.

摘要翻译： 提供了制造闪存器件的方法，其可以防止在单元栅极线之间发生短路。 制造这种闪存器件的方法可以包括形成包括一系列多单元栅极线和多个选择栅极线的栅极线。 每个栅极线可以包括全部形成在半导体衬底上的隧道绝缘层，浮动栅极，栅极绝缘层和/或可操作为控制栅极的多晶硅层的堆叠结构。 方法可以包括形成第一绝缘层，其选择性地从底部向上和相邻的单元栅极线和选择栅极线之间填充单元栅极线之间的间隙，并且不填充位于选择栅极的外侧的空间 与多个单元栅极线相对的线。 在形成第一绝缘层之后，可以在选择栅极线的与单元栅极线相对的外侧上形成间隔物。 可以在形成间隔物的空间中形成第二绝缘层。

公开(公告)号：US20100167490A1

公开(公告)日：2010-07-01

申请号：US12629920

申请日：2009-12-03

申请人： Jong-wan Choi ,  Yong-soon Choi ,  Bo-young Lee ,  Eunkee Hong ,  Eun-kyung Baek ,  Ju-seon Goo

发明人： Jong-wan Choi ,  Yong-soon Choi ,  Bo-young Lee ,  Eunkee Hong ,  Eun-kyung Baek ,  Ju-seon Goo

IPC分类号： H01L21/762

CPC分类号： H01L27/11521 ,  H01L27/11524

摘要： Provided are methods of fabricating flash memory devices that may prevent a short circuit from occurring between cell gate lines. Methods of fabricating such flash memory devices may include forming gate lines including a series of multiple cell gate lines and multiple selection gate lines. Each gate line may include a stacked structure of a tunnel insulating layer, a floating gate, a gate insulating layer, and/or a polysilicon layer operable to be a control gate, all formed on a semiconductor substrate. Methods may include forming a first insulating layer that selectively fills gaps between the cell gate lines from the bottom up and between adjacent ones of the cell gate lines and the selection gate lines, and does not fill a space located on outer sides of the selection gate lines that are opposite the plurality of cell gate lines. A spacer may be formed on the outer sides of the selection gate lines that are opposite to the cell gate lines, after forming the first insulating layer. A second insulating layer may be formed in a space where the spacer is formed.

摘要翻译： 提供了制造闪存器件的方法，其可以防止在单元栅极线之间发生短路。 制造这种闪存器件的方法可以包括形成包括一系列多单元栅极线和多个选择栅极线的栅极线。 每个栅极线可以包括全部形成在半导体衬底上的隧道绝缘层，浮动栅极，栅极绝缘层和/或可操作为控制栅极的多晶硅层的堆叠结构。 方法可以包括形成第一绝缘层，其选择性地从底部向上和相邻的单元栅极线和选择栅极线之间填充单元栅极线之间的间隙，并且不填充位于选择栅极的外侧的空间 与多个单元栅极线相对的线。 在形成第一绝缘层之后，可以在选择栅极线的与单元栅极线相对的外侧上形成间隔物。 可以在形成间隔物的空间中形成第二绝缘层。

公开(公告)号：US20110306195A1

公开(公告)日：2011-12-15

申请号：US13099485

申请日：2011-05-03

申请人： Jin-Gyun Kim ,  Bo-Young Lee ,  Ki-Hyun Hwang ,  Eunkee Hong ,  Jong-Wan Choi

发明人： Jin-Gyun Kim ,  Bo-Young Lee ,  Ki-Hyun Hwang ,  Eunkee Hong ,  Jong-Wan Choi

IPC分类号： H01L21/28

CPC分类号： H01L27/11578 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

摘要： In a vertical semiconductor device and a method of manufacturing a vertical semiconductor device, sacrificial layers and insulating interlayers are repeatedly and alternately stacked on a substrate. The sacrificial layers include boron (B) and nitrogen (N) and have an etching selectivity with respect to the insulating interlayers. Semiconductor patterns are formed on the substrate through the sacrificial layers and the insulating interlayers. The sacrificial layers and the insulating interlayers are at least partially removed between the semiconductor patterns to form sacrificial layer patterns and insulating interlayer patterns on sidewalls of the semiconductor patterns. The sacrificial layer patterns are removed to form grooves between the insulating interlayer patterns. The grooves expose portions of the sidewalls of the semiconductor patterns. A gate structure is formed in each of the grooves.

摘要翻译： 在垂直半导体器件和制造垂直半导体器件的方法中，牺牲层和绝缘夹层重叠交替堆叠在衬底上。 牺牲层包括硼（B）和氮（N），并且相对于绝缘夹层具有蚀刻选择性。 通过牺牲层和绝缘夹层在衬底上形成半导体图案。 在半导体图案之间至少部分去除牺牲层和绝缘夹层，以在半导体图案的侧壁上形成牺牲层图案和绝缘层间图案。 去除牺牲层图案以在绝缘层间图案之间形成凹槽。 凹槽暴露半导体图案的侧壁的部分。 在每个槽中形成栅极结构。

公开(公告)号：US08367535B2

公开(公告)日：2013-02-05

申请号：US13053668

申请日：2011-03-22

申请人： Yong-Soon Choi ,  Ha-Young Yi ,  Gil-Heyun Choi ,  Eunkee Hong ,  Sang-Hoon Ahn

发明人： Yong-Soon Choi ,  Ha-Young Yi ,  Gil-Heyun Choi ,  Eunkee Hong ,  Sang-Hoon Ahn

IPC分类号： H01L21/28

CPC分类号： H01L21/28052 ,  H01L21/28273 ,  H01L21/76834 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/7881

摘要： Example embodiments herein relate to a method of fabricating a semiconductor device. The method may include forming a liner insulating layer on a surface of a gate pattern to have a first thickness. Subsequently, a gap fill layer may be formed on the liner insulating layer by flowable chemical vapor deposition (FCVD) or spin-on-glass (SOG). The liner insulating layer and the gap fill layer may be recessed such that the liner insulating layer has a second thickness, which is smaller than the first thickness, in the region in which a metal silicide will be formed. Metal silicide may be formed on the plurality of gate patterns to have a relatively uniform thickness using the difference in thickness of the liner insulating layer.

摘要翻译： 本文的示例性实施例涉及制造半导体器件的方法。 该方法可以包括在栅极图案的表面上形成具有第一厚度的衬里绝缘层。 随后，可以通过可流动化学气相沉积（FCVD）或旋涂玻璃（SOG）在衬垫绝缘层上形成间隙填充层。 衬垫绝缘层和间隙填充层可以凹入，使得衬垫绝缘层在其中将形成金属硅化物的区域中具有小于第一厚度的第二厚度。 可以使用衬垫绝缘层的厚度差，在多个栅极图案上形成金属硅化物以具有相对均匀的厚度。

公开(公告)号：US20110281427A1

公开(公告)日：2011-11-17

申请号：US13053668

申请日：2011-03-22

申请人： Yong-Soon Choi ,  Ha-Young Yi ,  Gil-Heyun Choi ,  Eunkee Hong ,  Sang-Hoon Ahn

发明人： Yong-Soon Choi ,  Ha-Young Yi ,  Gil-Heyun Choi ,  Eunkee Hong ,  Sang-Hoon Ahn

IPC分类号： H01L21/28

CPC分类号： H01L21/28052 ,  H01L21/28273 ,  H01L21/76834 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/7881

摘要： Example embodiments herein relate to a method of fabricating a semiconductor device. The method may include forming a liner insulating layer on a surface of a gate pattern to have a first thickness. Subsequently, a gap fill layer may be formed on the liner insulating layer by flowable chemical vapor deposition (FCVD) or spin-on-glass (SOG). The liner insulating layer and the gap fill layer may be recessed such that the liner insulating layer has a second thickness, which is smaller than the first thickness, in the region in which a metal silicide will be formed. Metal silicide may be formed on the plurality of gate patterns to have a relatively uniform thickness using the difference in thickness of the liner insulating layer.

摘要翻译： 本文的示例性实施例涉及制造半导体器件的方法。 该方法可以包括在栅极图案的表面上形成具有第一厚度的衬里绝缘层。 随后，可以通过可流动化学气相沉积（FCVD）或旋涂玻璃（SOG）在衬垫绝缘层上形成间隙填充层。 衬垫绝缘层和间隙填充层可以凹入，使得衬垫绝缘层在其中将形成金属硅化物的区域中具有小于第一厚度的第二厚度。 可以使用衬垫绝缘层的厚度差，在多个栅极图案上形成金属硅化物以具有相对均匀的厚度。

公开(公告)号：US20100203700A1

公开(公告)日：2010-08-12

申请号：US12686638

申请日：2010-01-13

申请人： Kyungmun Byun ,  Deok-Young Jung ,  Ju-Seon Goo ,  Eunkee Hong

发明人： Kyungmun Byun ,  Deok-Young Jung ,  Ju-Seon Goo ,  Eunkee Hong

IPC分类号： H01L21/762

CPC分类号： H01L21/76224 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76837

摘要： A method of forming a semiconductor device includes preparing a substrate having a recessed area. A silicon oxide layer is formed at the recessed area. A catalytic nitridation treatment is performed for an upper portion of the silicon oxide layer to form a nitridation reactant on the upper portion of the silicon oxide layer. A dielectric layer is formed on the silicon oxide layer where the nitridation reactant is formed. The dielectric layer is annealed. According to the foregoing method, recession of the dielectric layer is prevented to fabricate a high-quality semiconductor device.

摘要翻译： 形成半导体器件的方法包括制备具有凹陷区域的衬底。 在凹陷区域形成氧化硅层。 对氧化硅层的上部进行催化氮化处理，以在氧化硅层的上部形成氮化反应物。 在形成氮化反应物的氧化硅层上形成介电层。 电介质层退火。 根据上述方法，防止了电介质层的凹陷以制造高质量的半导体器件。

公开(公告)号：US20060089008A1

公开(公告)日：2006-04-27

申请号：US11259408

申请日：2005-10-26

申请人： Eunkee Hong ,  Ju-Seon Goo ,  Kyu-Tae Na ,  Sang-Ho Rha

发明人： Eunkee Hong ,  Ju-Seon Goo ,  Kyu-Tae Na ,  Sang-Ho Rha

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/76232 ,  H01L21/02164 ,  H01L21/02222 ,  H01L21/02282 ,  H01L21/02337 ,  H01L21/3125 ,  H01L21/316

摘要： Methods of manufacturing silicon oxide layers for semiconductor devices are provided in which a substrate having a recess is coated with a spin-on-glass film so that the recess is filled with the spin-on-glass film. A main thermal treatment is performed on the spin-on-glass film at about 600 to about 1,000° C. at about 1 ATM to about 50 ATM so that the spin-on-glass film is converted into a relatively dense silicon oxide layer.

摘要翻译： 提供了制造用于半导体器件的氧化硅层的方法，其中具有凹陷的衬底涂覆有旋涂玻璃膜，使得凹部填充有旋涂玻璃膜。 在旋转玻璃膜上进行主要的热处理，在约1 00至约1000℃，约1个ATM至约50个ATM处进行，以使旋涂玻璃膜转化成相对致密的氧化硅层。

公开(公告)号：US20120034757A1

公开(公告)日：2012-02-09

申请号：US13162050

申请日：2011-06-16

申请人： Yong-Soon Choi ,  Jun-Won Lee ,  Gil-Heyun Choi ,  Eunkee Hong ,  Hong-Gun Kim ,  Ha-Young Yi

发明人： Yong-Soon Choi ,  Jun-Won Lee ,  Gil-Heyun Choi ,  Eunkee Hong ,  Hong-Gun Kim ,  Ha-Young Yi

IPC分类号： H01L21/762

CPC分类号： H01L21/76229 ,  H01L21/02222 ,  H01L21/02271 ,  H01L21/76885 ,  H01L27/105 ,  H01L27/10897 ,  H01L27/11531 ,  H01L27/11548

摘要： A method of fabricating a semiconductor device includes forming a first trench and a second trench in a semiconductor substrate, forming a first insulator to completely fill the first trench, the first insulator covering a bottom surface and lower sidewalls of the second trench and exposing upper sidewalls of the second trench, and forming a second insulator on the first insulator in the second trench.

摘要翻译： 制造半导体器件的方法包括在半导体衬底中形成第一沟槽和第二沟槽，形成第一绝缘体以完全填充第一沟槽，第一绝缘体覆盖第二沟槽的底表面和下侧壁，并暴露上侧壁 并且在所述第二沟槽中的所述第一绝缘体上形成第二绝缘体。