公开(公告)号：US07212512B2

公开(公告)日：2007-05-01

申请号：US10113743

申请日：2002-04-02

申请人： L. Victor Lucas ,  Carl F. Andren

发明人： L. Victor Lucas ,  Carl F. Andren

IPC分类号： H04Q7/24

CPC分类号： H03J7/065

摘要： A wireless transceiver including an oscillator, a radio, a baseband processor and MAC device that performs apiori frequency offset correction. The radio converts between RF signals and baseband signals. The baseband processor includes a frequency correction loop, an inverter and a combiner. The frequency correction loop generates a frequency offset signal based on a frequency difference between an oscillator reference frequency and frequency of a received signal. The inverter inverts the frequency offset signal and the combiner adjusts frequency of a transmit signal by the inverted frequency offset signal. The MAC processes received packets, identifies packets received from an AP, provides packets to the baseband processor for transmission, and controls the baseband processor to adjust transmit signals to a frequency of the AP. The baseband processor may include a memory or filter to store or update frequency offset values.

摘要翻译： 一种无线收发器，包括执行apiopi频偏校正的振荡器，无线电，基带处理器和MAC设备。 无线电在RF信号和基带信号之间进行转换。 基带处理器包括频率校正回路，逆变器和组合器。 频率校正循环基于振荡器参考频率和接收信号的频率之间的频率差产生频率偏移信号。 逆变器反相频率偏移信号，组合器通过反相频率偏移信号调整发射信号的频率。 MAC处理接收到的分组，识别从AP接收的分组，向基带处理器提供分组以进行传输，并控制基带处理器将发射信号调整到AP的频率。 基带处理器可以包括用于存储或更新频率偏移值的存储器或滤波器。

公开(公告)号：US4707839A

公开(公告)日：1987-11-17

申请号：US535923

申请日：1983-09-26

申请人： Carl F. Andren ,  David A. Olaker

发明人： Carl F. Andren ,  David A. Olaker

IPC分类号： H04B1/707 ,  H04B1/7093 ,  H04K1/02

CPC分类号： H04B1/7093 ,  H04B1/707

摘要： In a spread spectrum communications system employing cyclic code shift keying as its primary modulation, the transmission waveform is spread for transmission security by modulo-2 adding a pseudo-noise sequence to the CCSK data symbols prior to phase modulating onto a carrier signal for transmission. If the transmission modulation is minimum shift keying (MSK) the two components of the data stream are applied to the carrier with a differential encoding step implicit in the modulation scheme. This differential encoding characteristic makes stripping of the PN spread function prior to CCSK demodulation difficult at the receiving end. In order to demodulate this waveform in an optimum manner, an array correlator, the adjacent correlator stages of which have one chip relative time displacements of their CCSK reference waveform, is employed. In effect the array correlator becomes a parallel array of matched filters matched to each cyclic shift of the incoming waveform. By modulo-2 addition of the PN spreading waveform with the time displaced CCSK reference waveform in each stage of the correlator, the correlator can be made to match all versions of the spread symbol being received.

摘要翻译： 在采用循环码移键控作为其一次调制的扩展频谱通信系统中，通过在相位调制之前的CCSK数据符号上加模拟噪声序列，将传输波形扩展为传输安全性，以传输载波信号。 如果传输调制是最小移位键控（MSK），则数据流的两个分量以调制方案中隐含的差分编码步骤应用于载波。 该差分编码特性使得在接收端难以解码CCSK解调之前的PN扩展功能。 为了以最佳的方式解调该波形，采用阵列相关器，其相邻的相关器级具有其CCSK参考波形的一个码片相对时间位移。 实际上，阵列相关器成为与输入波形的每个循环移位相匹配的匹配滤波器的并行阵列。 通过在相关器的每个级中随时间移位CCSK参考波形的PN扩展波形的模2加法，可以使相关器匹配所接收的扩展符号的所有版本。

公开(公告)号：US4538280A

公开(公告)日：1985-08-27

申请号：US492021

申请日：1983-05-05

申请人： William H. Mosley, Jr. ,  Carl F. Andren

发明人： William H. Mosley, Jr. ,  Carl F. Andren

IPC分类号： H04B1/707 ,  H03D1/22

CPC分类号： H04B1/70712

摘要： A detector (20) is provided for use in a communication receiver where a received spread spectrum data signal is detected using a locally generated reference signal to decode the data signal. The detector (20) includes first (22) and second channels (24) and circuitry (90) for applying the received encoded data signal to the first (22) and second channels (24). A local generator (50) is provided for generating the reference signal wherein the reference signal has polarity transitions. A demodulator (40) is included in the first channel (22) for generating a detected recovered data signal from the received data signal in response to the reference signal. Circuitry (52) is provided for detecting the polarity transitions in the reference signal and for generating a differential PN signal. Circuitry (42) is further provided in the second channel (24) for correlating the received data signal and the differential PN signal to thereby generate a recovered error signal. The recovered data signal and the recovered error signal are correlated by circuitry (58) to generate a control signal for application to the local generator (50) for locking the reference signal to a component of the received data signal.

摘要翻译： 提供了一种检测器（20），用于在通信接收机中使用本地产生的参考信号来检测接收的扩展频谱数据信号以对数据信号进行解码。 检测器（20）包括用于将接收到的编码数据信号施加到第一通道（22）和第二通道（24）的第一通道（22）和第二通道（24）和电路（90）。 本地发生器（50）被提供用于产生参考信号，其中参考信号具有极性转换。 解调器（40）包括在第一通道（22）中，用于响应于参考信号从接收的数据信号产生检测到的恢复数据信号。 提供电路（52）用于检测参考信号中的极性转换并产生差分PN信号。 电路（42）还被提供在第二通道（24）中，用于使接收的数据信号和差分PN信号相关，从而产生恢复的误差信号。 恢复的数据信号和恢复的误差信号通过电路（58）相关，以产生用于施加到本地发生器（50）的控制信号，用于将参考信号锁定到所接收的数据信号的分量。

公开(公告)号：US4234966A

公开(公告)日：1980-11-18

申请号：US15231

申请日：1979-02-26

申请人： William H. Mosley, Jr. ,  Carl F. Andren

发明人： William H. Mosley, Jr. ,  Carl F. Andren

IPC分类号： H03D7/14 ,  H04B1/26

CPC分类号： H03D7/1408

摘要： A direct current responsive mixing circuit (10) includes three mixers (14, 16 & 18), each having one D.C. port and two A.C. ports. The D.C. ports are responsive to D.C. and A.C. signals, while the A.C. ports are responsive only to A.C. signals. One mixer (14) has an A.C. port (24) receiving a pump signal and a D.C. port (28) receiving an I input signal. A second mixer (16) has an A.C. port (26) receiving the pump signal and a D.C. port (32) receiving a Q input signal. The remaining A.C. ports of the first two mixers (14 and 16) are connected to the two A.C. ports (36 and 38) of the third mixer (18). An output signal having a component corresponding to the product of the I and Q input signals is produced at the D.C. port (40) of the third mixer (18). In this construction, the mixing circuit 10 is responsive to A.C. and D.C. input signals and may produce a D.C. output signal component.

摘要翻译： 直流响应混合电路（10）包括三个混频器（14,16和18），每个具有一个直流端口和两个交流端口。 直流端口响应于直流和交流信号，而交流端口仅响应交流信号。 一个混合器（14）具有接收泵浦信号的交流端口（24）和接收I输入信号的直流端口（28）。 第二混合器（16）具有接收泵浦信号的交流端口（26）和接收Q输入信号的直流端口（32）。 前两个混合器（14和16）的剩余交流端口连接到第三混合器（18）的两个交流端口（36和38）。 具有对应于I和Q输入信号的乘积的分量的输出信号在第三混频器（18）的直流端（40）产生。 在这种结构中，混合电路10响应于交流输入和直流输入信号，并可产生直流输出信号分量。

公开(公告)号：US06690715B2

公开(公告)日：2004-02-10

申请号：US09823845

申请日：2001-03-30

申请人： Mark A. Webster ,  George R. Nelson ,  Karen W. Halford ,  Carl F. Andren

发明人： Mark A. Webster ,  George R. Nelson ,  Karen W. Halford ,  Carl F. Andren

IPC分类号： H04J13104

CPC分类号： H04B1/7105 ,  H04B1/7093 ,  H04B1/7115 ,  H04L25/03057 ,  H04L2025/03375 ,  H04L2025/03401 ,  H04L2025/0349

摘要： The performance of a RAKE receiver for indoor multipath WLAN applications on direct sequence spread spectrum signals having relatively short codeword lengths is enhanced by embedding a decision feedback equalizer structure in the signal processing path through the receiver's channel matched filter and codeword correlator. The decision feedback equalizer serves to cancel both inter-codeword interference (ISI) or “bleed-over” between codewords, and intra-codeword chip interference (ICI) or smearing of the energy within the chips of a respective codeword.

摘要翻译： 通过在信号处理路径中通过接收机的信道匹配滤波器和码字相关器嵌入判决反馈均衡器结构，增强了具有相对短的码字长度的直接序列扩频信号上用于室内多路径WLAN应用的RAKE接收机的性能。 判决反馈均衡器用于消除码字之间的码间干扰（ISI）或“渗漏”，以及相应码字的码片内的码内码片干扰（ICI）或能量的拖尾。

公开(公告)号：US5029184A

公开(公告)日：1991-07-02

申请号：US470199

申请日：1990-01-24

申请人： Carl F. Andren ,  Leonard V. Lucas ,  John A. Schachte

发明人： Carl F. Andren ,  Leonard V. Lucas ,  John A. Schachte

IPC分类号： H04K3/00

CPC分类号： H04K3/226 ,  H04K3/25

摘要： A low probability of intercept communication system (CCSK)--modulates information signals onto an inverse fast Fourier transformation of a large number of simultaneous frequencies that have been determined to be reasonably `quiet` within a given system bandwidth, so as to produce a time domain pulse waveform. The amplitude of each transmitted frequency is weighted. Within the receiver equipment of each participant in the system, the incoming pulse waveform produced by the inverse fast Fourier transformation mechanism at the source is coupled to a fast Fourier transform operator, so as to separate the time domain signal into a plurality of frequency components that contain the modulated data. These components are then convolved with a replica of the plurality of quiet channels to derive a time domain output waveform from which the data modulation can be identified and recovered. Even if a jamming threat is injected into one or more of the `quiet` channels that has been selected as a participating carrier, by virtue of the signal analysis and recovery process employed by each unit for incoming signals, jamming spikes are effectively excised.

摘要翻译： 拦截通信系统（CCSK）的低概率 - 将信息信号调制到已经被确定为在给定系统带宽内合理“安静”的大量同时频率的快速傅里叶逆变换，从而产生时域 脉搏波形。 每个发射频率的幅度被加权。 在系统中每个参与者的接收机设备内，由源上的快速傅里叶逆变换机构产生的输入脉冲波形耦合到快速傅里叶变换算子，以将时域信号分离成多个频率分量， 包含调制数据。 然后将这些组件与多个安静信道的副本进行卷积，以导出可以识别和恢复数据调制的时域输出波形。 即使将干扰威胁注入一个或多个已经被选为参与载体的“安静”信道，由于每个单元用于输入信号的信号分析和恢复过程，有效地切断了干扰峰值。

公开(公告)号：US4348641A

公开(公告)日：1982-09-07

申请号：US110462

申请日：1980-01-08

申请人： Lex A. Scott ,  William H. Mosley, Jr. ,  Carl F. Andren

发明人： Lex A. Scott ,  William H. Mosley, Jr. ,  Carl F. Andren

IPC分类号： H04L27/22 ,  H04L27/00 ,  H04L27/227 ,  H04L27/233 ,  H03D3/00 ,  H03K9/00

CPC分类号： H04L27/2273 ,  H04L27/2332 ,  H04L2027/0057

摘要： A recovery loop includes an analog circuit that mixes a fixed frequency signal from a temperature controlled oscillator (20) with an IF input to produce product signals corresponding to the quadrature components of data signals with frequency offset. A digital complex multiplier (32) is responsive to the product signals and to the output of a number controlled oscillator (34) to produce a digital output corresponding to the data signals. The output of the number controlled oscillator (34) is controlled by a digital phase lock loop.

摘要翻译： 恢复回路包括将来自温度控制振荡器（20）的固定频率信号与IF输入混合的模拟电路，以产生对应于具有频率偏移的数据信号的正交分量的乘积信号。 数字复数乘法器（32）响应于产品信号和数字控制振荡器（34）的输出，以产生对应于数据信号的数字输出。 数字控制振荡器（34）的输出由数字锁相环控制。

公开(公告)号：US4238739A

公开(公告)日：1980-12-09

申请号：US15233

申请日：1979-02-26

申请人： William H. Mosley ,  Carl F. Andren ,  Lex Scott

发明人： William H. Mosley ,  Carl F. Andren ,  Lex Scott

IPC分类号： H03L7/113 ,  H04L27/00 ,  H04L27/227 ,  H03L7/10

CPC分类号： H04L27/2273 ,  H03L7/113 ,  H04L2027/0067

摘要： A phase lock loop (10) includes a frequency and phase preset network for presetting a local oscillator (20) in substantial synchronism with a carrier signal. The preset network utilizes time delayed output signals from split or double correlators (32, 34, 36, 38) to determine a change in the phase angle between the local oscillator signal and the carrier signal for a known time period to determine the frequency of the local oscillator signal relative to the carrier signal frequency. The preset network determines the phase of the local oscillator signal relative to the carrier signal phase utilizing the summed output of one split correlator (32 and 34) and of another split correlator (36 and 38).

摘要翻译： 锁相环（10）包括频率和相位预设网络，用于与载波信号基本上同步地预置本地振荡器（20）。 预设网络利用来自分离或双相关器（32,34,36,38）的时间延迟输出信号来确定本地振荡器信号和载波信号之间的相位角在已知时间段内的变化，以确定 本地振荡器信号相对于载波信号频率。 预设网络利用一个分裂相关器（32和34）和另一个分裂相关器（36和38）的相加输出来确定本地振荡器信号相对于载波信号相位的相位。

公开(公告)号：US06233273B1

公开(公告)日：2001-05-15

申请号：US09342583

申请日：1999-06-29

申请人： Mark A. Webster ,  George R. Nelson ,  Karen W. Halford ,  Carl F. Andren

发明人： Mark A. Webster ,  George R. Nelson ,  Karen W. Halford ,  Carl F. Andren

IPC分类号： H04B1500

CPC分类号： H04B1/7105 ,  H04B1/7093 ,  H04B1/7115 ,  H04L25/03057 ,  H04L2025/03375 ,  H04L2025/03401 ,  H04L2025/0349

摘要： The performance of a RAKE receiver for indoor multipath WLAN applications on direct sequence spread spectrum signals having relatively short codeword lengths is enhanced by embedding a decision feedback equalizer structure in the signal processing path through the receiver's channel matched filter and codeword correlator. The decision feedback equalizer serves to cancel both inter-codeword interference (ISI) or ‘bleed-over’ between codewords, and intra-codeword chip interference (ICI) or smearing of the energy within the chips of a respective codeword.

摘要翻译： 通过在信号处理路径中通过接收机的信道匹配滤波器和码字相关器嵌入判决反馈均衡器结构，增强了具有相对短的码字长度的直接序列扩频信号上用于室内多路径WLAN应用的RAKE接收机的性能。 判决反馈均衡器用于消除码字之间的码间干扰（ISI）或“渗漏”，以及相应码字的码片内的码内码片干扰（ICI）或能量的拖延。

公开(公告)号：US5654991A

公开(公告)日：1997-08-05

申请号：US509588

申请日：1995-07-31

申请人： Carl F. Andren ,  Leonard Victor Lucas ,  John C. Fakatselis ,  Jim Snell

发明人： Carl F. Andren ,  Leonard Victor Lucas ,  John C. Fakatselis ,  Jim Snell

IPC分类号： H04L25/40 ,  H04L7/02 ,  H04L7/08 ,  H04L7/00

CPC分类号： H04B1/70755 ,  H04L7/0054 ,  H04B2201/70707

摘要： In a direct sequence spread spectrum receiver, an apparatus for obtaining and adjusting bit synchronization. In one aspect, the bit synchronization is adjusted by selectively inverting a clocking circuit to delay sampling by one-half a clock cycle and to combine the inversion with a skipping of one cycle to advance the sampling by one-half cycle. In another aspect of the invention, the synchronization circuit avoids overflow of accumulating components by downshifting both the partial sums and the input data when needed.

摘要翻译： 在直接序列扩频接收机中，用于获取和调整比特同步的装置。 在一个方面，通过选择性地反相时钟电路来调整比特同步，以将采样延迟半个时钟周期，并将反演与一个周期的跳过组合，以将采样推进半个周期。 在本发明的另一方面，同步电路通过在需要时降低部分和数据和输入数据来避免积累分量的溢出。