公开(公告)号：US20170186781A1

公开(公告)日：2017-06-29

申请号：US15245944

申请日：2016-08-24

Applicant: LG DISPLAY CO., LTD.

Inventor： Soyoung NOH ,  Jinchae JEON ,  Seungchan CHOI ,  Junho LEE ,  Youngjang LEE ,  Sungbin RYU ,  Kitae KIM ,  Bokyoung CHO ,  Jeanhan YOON ,  Uijin CHUNG ,  Jihye LEE ,  Eunsung KIM ,  Hyunsoo SHIN ,  Kyeongju MOON ,  Hyojin KIM ,  Wonkyung KIM ,  Jeihyun LEE ,  Soyeon JE

IPC: H01L27/12 ,  H01L49/02 ,  H01L29/417

CPC classification number: H01L27/1248 ,  H01L27/1225 ,  H01L27/1251 ,  H01L27/1255 ,  H01L27/1288 ,  H01L27/3258 ,  H01L27/3262 ,  H01L28/60 ,  H01L29/41733 ,  H01L29/78675 ,  H01L29/7869

Abstract: A thin film transistor substrate having two different types of thin film transistors on the same substrate, and a display using the same are discussed. The thin film transistor substrate can include a substrate, a first thin film transistor (TFT), a second TFT, a first storage capacitor electrode, an oxide layer, a nitride layer, a second storage capacitor electrode, a planar layer and a pixel electrode. The first TFT is disposed in a first area, the second TFT is disposed in a second area, and the first storage capacitor electrode is disposed in a third area on the substrate respectively. The oxide layer covers the first and second TFTs, and exposes the first storage capacitor electrode. The nitride layer is disposed on the oxide layer and covers the first storage capacitor electrode. The second storage capacitor electrode overlaps with the first storage capacitor electrode on the nitride layer. The planar layer covers the first and second TFTs,and the second storage capacitor electrode. The pixel electrode is disposed on the planar layer.

公开(公告)号：US20180350848A1

公开(公告)日：2018-12-06

申请号：US16047875

申请日：2018-07-27

Applicant: LG Display Co., Ltd.

Inventor： Hyunsoo SHIN ,  Uijin CHUNG

IPC: H01L27/12 ,  H01L29/786

CPC classification number: H01L27/1251 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/1248 ,  H01L27/127 ,  H01L29/78675 ,  H01L29/7869 ,  H01L29/78696

Abstract: A thin film transistor substrate includes a substrate; a first thin film transistor on the substrate and including a polycrystalline semiconductor layer, a first gate electrode on the polycrystalline semiconductor layer, a first source electrode, and a first drain electrode; a second thin film transistor on the substrate and including a second gate electrode, an oxide semiconductor layer on the second gate electrode, a second source electrode, and a second drain electrode; an intermediate insulating layer on the first gate electrode and the second gate electrode and under the oxide semiconductor layer; and a dummy layer between the first source electrode and the intermediate insulating layer and between the first drain electrode and the intermediate insulating layer, wherein the dummy layer is formed of a same material as the oxide semiconductor layer.

公开(公告)号：US20160307936A1

公开(公告)日：2016-10-20

申请号：US15133419

申请日：2016-04-20

Applicant: LG Display Co., Ltd.

Inventor： Hyunsoo SHIN ,  Uijin CHUNG

IPC: H01L27/12 ,  H01L29/786

CPC classification number: H01L27/1251 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/1248 ,  H01L27/127 ,  H01L29/78675 ,  H01L29/7869 ,  H01L29/78696

Abstract: A thin film transistor substrate includes a substrate; a first thin film transistor on the substrate and including a polycrystalline semiconductor layer, a first gate electrode on the polycrystalline semiconductor layer, a first source electrode, and a first drain electrode; a second thin film transistor on the substrate and including a second gate electrode, an oxide semiconductor layer on the second gate electrode, a second source electrode, and a second drain electrode; an intermediate insulating layer on the first gate electrode and the second gate electrode and under the oxide semiconductor layer; and a dummy layer between the first source electrode and the intermediate insulating layer and between the first drain electrode and the intermediate insulating layer, wherein the dummy layer is formed of a same material as the oxide semiconductor layer.

Abstract translation: 薄膜晶体管基板包括基板; 在所述基板上的第一薄膜晶体管，包括多晶半导体层，所述多晶半导体层上的第一栅电极，第一源电极和第一漏电极; 第二薄膜晶体管，其包括第二栅电极，第二栅电极上的氧化物半导体层，第二源电极和第二漏电极; 在所述第一栅极电极和所述第二栅极电极之下和所述氧化物半导体层下方的中间绝缘层; 以及在第一源极和中间绝缘层之间以及第一漏极和中间绝缘层之间的虚设层，其中虚设层由与氧化物半导体层相同的材料形成。