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公开(公告)号：US09077378B2
公开(公告)日：2015-07-07
申请号：US13755757
申请日：2013-01-31
Applicant: LSI Corporation
Inventor： YingQuan Wu
CPC classification number: H03M13/1128 , H03M13/1102 , H03M13/1117 , H03M13/13 , H03M13/152 , H03M13/255 , H03M13/2707 , H03M13/2942
Abstract: Methods and apparatus are provided for integrated-interleaved Low Density Parity Check (LDPC) coding and decoding. Integrated-interleaved LDPC encoding is performed by obtaining at least a first data element and a second data element; systematically encoding the at least first data element using a submatrix H0 of a sparse parity check matrix H1 to obtain at least a first codeword; truncating the at least first data element to obtain at least a first truncated data element; systematically encoding the at least second data element and the at least first truncated data element using the sparse parity check matrix H1 to obtain a nested codeword; and generating a second codeword based at least in part on a combination of the first codeword and the nested codeword. Integrated-interleaved LDPC decoding is also provided.
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公开(公告)号：US20130297988A1
公开(公告)日：2013-11-07
申请号：US13753987
申请日：2013-01-30
Applicant: LSI CORPORATION
Inventor： YingQuan Wu , Earl T. Cohen
IPC: G06F11/10
CPC classification number: G06F11/1068 , G06F11/1048 , G06F12/00 , H03M13/1102
Abstract: Described embodiments provide a media controller that performs error correction on data read from a solid-state media. The media controller receives a read operation from a host device to read one or more given read units of the solid-state media. The media controller reads the data for the corresponding read units from the solid-state media employing initial values for one or more read threshold voltages. Only if a disparity between an actual number of bits at a given logic level included in the read data and an expected number of bits at the given logic level included in the read data has not reached a predetermined threshold, the media controller decodes the read data and provides the decoded data to the host device.
Abstract translation: 描述的实施例提供了对从固态介质读取的数据执行错误校正的介质控制器。 媒体控制器从主机设备接收读取操作以读取固态介质的一个或多个给定读取单元。 媒体控制器使用采用初始值的一个或多个读取阈值电压从固态介质读取相应读取单元的数据。 只有在包含在读取数据中的给定逻辑电平的实际位数与读取数据中包含的给定逻辑电平之间的预期位数之间的差异尚未达到预定阈值时，媒体控制器解码读取的数据 并将解码的数据提供给主机设备。
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3.发明申请Generating Partially Sparse Generator Matrix for a Quasi-Cyclic Low-Density Parity-Check Encoder 有权生成准循环低密度奇偶校验编码器的部分稀疏发生器矩阵公开(公告)号：US20140298129A1
公开(公告)日：2014-10-02
申请号：US13852852
申请日：2013-03-28
Applicant: LSI CORPORATION
Inventor： YingQuan Wu , Ivana Djurdjevic , Alexander Hubris
IPC: H03M13/13
CPC classification number: H03M13/116 , H03M13/611 , H03M13/616
Abstract: A method and system for constructing a generator matrix is disclosed. The method includes: receiving a parity check matrix H, wherein the parity check matrix H includes multiple circulant sub-matrices; rearranging the parity check matrix H by column and row permutations to obtain a rearranged parity check matrix H′; and constructing the generator matrix G based on the rearranged parity check matrix H′.
Abstract translation: 公开了一种用于构建发电机矩阵的方法和系统。 该方法包括：接收奇偶校验矩阵H，其中奇偶校验矩阵H包括多个循环子矩阵; 通过列和行排列重排奇偶校验矩阵H以获得重新排列的奇偶校验矩阵H'; 以及基于重新排列的奇偶校验矩阵H'构建生成矩阵G.
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公开(公告)号：US09025393B2
公开(公告)日：2015-05-05
申请号：US13856179
申请日：2013-04-03
Applicant: LSI Corporation
Inventor： Yunxiang Wu , Zhengang Chen , YingQuan Wu , Ning Chen
CPC classification number: G11C11/5642 , G11C16/00 , G11C29/023 , G11C29/028 , G11C29/42 , G11C29/50004
Abstract: A method of optimizing solid state drive (SSD) soft retry voltages comprises limiting a number of voltage reads and properly spacing and determining the reference voltage at which each voltage is read based on desired Bit Error Rate (BER) and channel throughput. The method determines each reference voltage for a number of soft retry voltage reads based on a hard decision read. The spacing between each read reference voltage is constant since each SSD type requires a number of reads for an accurate presentation of soft retry voltages. The voltage distance between each successive read is limited to a multiple of the constant spacing while the multiple is based on success or failure of the first read. The method determines a limited number of reads, the constant spacing between reads, and a desired reference voltage for each read, thereby increasing valuable throughput of the channel and decreasing BER.
Abstract translation: 优化固态驱动（SSD）软重试电压的方法包括基于所需的误码率（BER）和信道吞吐量来限制多个电压读取和适当的间隔并确定读取每个电压的参考电压。 该方法基于硬判决读取确定多个软重试电压读取的每个参考电压。 每个读取参考电压之间的间距是恒定的，因为每个SSD类型需要多个读取以精确呈现软重试电压。 每个连续读取之间的电压距离被限制为恒定间隔的倍数，而倍数是基于第一次读取的成功或失败。 该方法确定读数的有限数量，读取之间的恒定间隔和每次读取的期望参考电压，从而增加了信道的有价值的吞吐量并降低了BER。
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公开(公告)号：US20140286102A1
公开(公告)日：2014-09-25
申请号：US13856179
申请日：2013-04-03
Applicant: LSI CORPORATION
Inventor： Yunxiang Wu , Zhengang Chen , YingQuan Wu , Ning Chen
IPC: G11C29/04
CPC classification number: G11C11/5642 , G11C16/00 , G11C29/023 , G11C29/028 , G11C29/42 , G11C29/50004
Abstract: A method of optimizing solid state drive (SSD) soft retry voltages comprises limiting a number of voltage reads and properly spacing and determining the reference voltage at which each voltage is read based on desired Bit Error Rate (BER) and channel throughput. The method determines each reference voltage for a number of soft retry voltage reads based on a hard decision read. The spacing between each read reference voltage is constant since each SSD type requires a number of reads for an accurate presentation of soft retry voltages. The voltage distance between each successive read is limited to a multiple of the constant spacing while the multiple is based on success or failure of the first read. The method determines a limited number of reads, the constant spacing between reads, and a desired reference voltage for each read, thereby increasing valuable throughput of the channel and decreasing BER.
Abstract translation: 优化固态驱动（SSD）软重试电压的方法包括基于所需的误码率（BER）和信道吞吐量来限制多个电压读取和适当的间隔并确定读取每个电压的参考电压。 该方法基于硬判决读取确定多个软重试电压读取的每个参考电压。 每个读取参考电压之间的间距是恒定的，因为每个SSD类型需要多个读取以精确呈现软重试电压。 每个连续读取之间的电压距离被限制为恒定间隔的倍数，而倍数是基于第一次读取的成功或失败。 该方法确定读数的有限数量，读取之间的恒定间隔和每次读取的期望参考电压，从而增加了信道的有价值的吞吐量并降低了BER。
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Patent Agency Ranking
公开(公告)号：US20150149840A1
公开(公告)日：2015-05-28
申请号：US14135837
申请日：2013-12-20
Applicant: LSI Corporation
CPC classification number: G11C16/28 , G11C11/5642 , G11C16/08 , G11C16/26 , G11C29/026 , G11C29/028 , G11C29/42 , G11C2029/4402 , H03M13/1117 , H03M13/1125
Abstract: An apparatus for reading a non-volatile memory includes a tracking module operable to calculate means and variances of voltage level distributions in a non-volatile memory and to calculate at least one reference voltage to be used when reading the non-volatile memory based on the means and variances, a likelihood generator operable to calculate at least one other reference voltage to be used when reading the non-volatile memory, wherein the at least one other reference voltage is based at least in part on a predetermined likelihood value constellation, and to map read patterns from the non-volatile memory to likelihood values, and a read controller operable to read the non-volatile memory using the at least one reference voltage and the at least one other reference voltage to yield the read patterns.
Abstract translation: 用于读取非易失性存储器的装置包括跟踪模块，其可操作以计算非易失性存储器中的电压电平分布的平均值和方差，并且计算当基于所述非易失性存储器读取非易失性存储器时要使用的至少一个参考电压 平均值和方差，似然发生器可操作以计算在读取非易失性存储器时要使用的至少一个其它参考电压，其中至少一个其它参考电压至少部分地基于预定似然值星座，并且 将从非易失性存储器读取图案映射到似然值，以及读取控制器，其可操作以使用所述至少一个参考电压和所述至少一个其它参考电压来读取所述非易失性存储器以产生所述读取模式。
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7.发明授权Generating partially sparse generator matrix for a quasi-cyclic low-density parity-check encoder 有权为准循环低密度奇偶校验编码器生成部分稀疏发生器矩阵公开(公告)号：US09037945B2
公开(公告)日：2015-05-19
申请号：US13852852
申请日：2013-03-28
Applicant: LSI Corporation
Inventor： YingQuan Wu , Ivana Djurdjevic , Alexander Hubris
CPC classification number: H03M13/116 , H03M13/611 , H03M13/616
Abstract: A method and system for constructing a generator matrix is disclosed. The method includes: receiving a parity check matrix H, wherein the parity check matrix H includes multiple circulant sub-matrices; rearranging the parity check matrix H by column and row permutations to obtain a rearranged parity check matrix H′; and constructing the generator matrix G based on the rearranged parity check matrix H′.
Abstract translation: 公开了一种用于构建发电机矩阵的方法和系统。 该方法包括：接收奇偶校验矩阵H，其中奇偶校验矩阵H包括多个循环子矩阵; 通过列和行排列重排奇偶校验矩阵H以获得重新排列的奇偶校验矩阵H'; 以及基于重新排列的奇偶校验矩阵H'构建生成矩阵G.
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公开(公告)号：US20150026536A1
公开(公告)日：2015-01-22
申请号：US13958162
申请日：2013-08-02
Applicant: LSI Corporation
Inventor： Alexander Hubris , Zhengang Chen , AbdelHakim S. Alhussien , YingQuan Wu
IPC: G06F11/10
CPC classification number: G06F11/1048 , G06F11/10 , H03M13/1102 , H03M13/1105 , H03M13/1137 , H03M13/114 , H03M13/1142 , H03M13/116 , H03M13/1171 , H03M13/6561 , H03M13/658
Abstract: A low density parity check decoder includes a variable node processor operable to generate variable node to check node messages and to calculate perceived values based on check node to variable node messages, a check node processor operable to generate the check node to variable node message vectors and to calculate checksums based on the variable node to check node messages, and a convergence detector and bit map generator operable to convergence of the perceived values and to generate at least one bit map that identifies variable nodes that are connected to check nodes with unsatisfied parity checks.
Abstract translation: 低密度奇偶校验解码器包括可变节点处理器，其可操作以生成可变节点以校验节点消息，并且基于对可变节点消息的校验节点来计算感知值;校验节点处理器，可操作以将校验节点生成到可变节点消息向量;以及 基于变量节点来计算校验和以检查节点消息;以及收敛检测器和位图生成器，其可操作用于感知值的收敛并生成至少一个位图，其识别连接到具有不满足奇偶校验检查的节点的变量节点 。
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公开(公告)号：US08938659B2
公开(公告)日：2015-01-20
申请号：US13753987
申请日：2013-01-30
Applicant: LSI Corporation
Inventor： YingQuan Wu , Earl T. Cohen
CPC classification number: G06F11/1068 , G06F11/1048 , G06F12/00 , H03M13/1102
Abstract: Described embodiments provide a media controller that performs error correction on data read from a solid-state media. The media controller receives a read operation from a host device to read one or more given read units of the solid-state media. The media controller reads the data for the corresponding read units from the solid-state media employing initial values for one or more read threshold voltages. Only if a disparity between an actual number of bits at a given logic level included in the read data and an expected number of bits at the given logic level included in the read data has not reached a predetermined threshold, the media controller decodes the read data and provides the decoded data to the host device.
Abstract translation: 描述的实施例提供了对从固态介质读取的数据执行错误校正的介质控制器。 媒体控制器从主机设备接收读取操作以读取固态介质的一个或多个给定读取单元。 媒体控制器使用采用初始值的一个或多个读取阈值电压从固态介质读取相应读取单元的数据。 只有在包含在读取数据中的给定逻辑电平的实际位数与读取数据中包含的给定逻辑电平之间的预期位数之间的差异尚未达到预定阈值时，媒体控制器解码读取的数据 并将解码的数据提供给主机设备。
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公开(公告)号：US20140215285A1
公开(公告)日：2014-07-31
申请号：US13755757
申请日：2013-01-31
Applicant: LSI CORPORATION
Inventor： YingQuan Wu
IPC: H03M13/13
CPC classification number: H03M13/1128 , H03M13/1102 , H03M13/1117 , H03M13/13 , H03M13/152 , H03M13/255 , H03M13/2707 , H03M13/2942
Abstract: Methods and apparatus are provided for integrated-interleaved Low Density Parity Check (LDPC) coding and decoding. Integrated-interleaved LDPC encoding is performed by obtaining at least a first data element and a second data element; systematically encoding the at least first data element using a submatrix H0 of a sparse parity check matrix H1 to obtain at least a first codeword; truncating the at least first data element to obtain at least a first truncated data element; systematically encoding the at least second data element and the at least first truncated data element using the sparse parity check matrix H1 to obtain a nested codeword; and generating a second codeword based at least in part on a combination of the first codeword and the nested codeword. Integrated-interleaved LDPC decoding is also provided.
Abstract translation: 提供了用于集成交织的低密度奇偶校验（LDPC）编码和解码的方法和装置。 通过获得至少第一数据元素和第二数据元素来执行集成交错LDPC编码; 使用稀疏奇偶校验矩阵H1的子矩阵H0对所述至少第一数据元素进行系统地编码以获得至少第一码字; 截断所述至少第一数据元素以获得至少第一截断数据元素; 使用稀疏奇偶校验矩阵H1对所述至少第二数据元素和所述至少第一截断数据元素进行系统地编码以获得嵌套代码字; 以及至少部分地基于所述第一码字和所述嵌套码字的组合来生成第二码字。 还提供了集成交错LDPC解码。
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