中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

9 records (took 0.013 seconds)

    Timing error detector with diversity loop detector decision feedback
    1.
    发明授权
    Timing error detector with diversity loop detector decision feedback 有权
    具有分集环路检测器判定反馈的定时误差检测器

    公开(公告)号：US09275655B2

    公开(公告)日：2016-03-01

    申请号：US13941464

    申请日：2013-07-13

    Applicant: LSI Corporation

    Inventor： Bruce Wilson ,  Yang Han ,  Yu Kou ,  Rui Cao

    IPC: G11B20/14 ,  G11B5/09 ,  G11B20/10

    CPC classification number: G11B5/09 ,  G11B20/10009 ,  G11B20/10046 ,  G11B20/10222 ,  G11B20/1403 ,  G11B2220/2516

    Abstract: Aspects of the disclosure pertain to an apparatus for detecting timing errors including an analog to digital converter circuit, a diversity loop detector and a timing error calculation circuit. The analog to digital converter circuit is operable to convert an input signal into a series of digital samples. The diversity loop detector is operable to apply a data detection algorithm to a plurality of signals derived from the series of digital samples at different phase offsets, to select one of the phase offsets, and to yield a detected output with the selected phase offset. The timing error calculation circuit is operable to calculate a timing error of the analog to digital converter circuit based at least in part on the selected phase offset.

    Abstract translation: 本公开的方面涉及用于检测定时误差的装置，包括模数转换器电路，分集环路检测器和定时误差计算电路。 模数转换器电路可操作以将输入信号转换为一系列数字采样。 分集环路检测器可操作以将数据检测算法应用于在不同相位偏移处从一系列数字样本导出的多个信号，以选择相位偏移中的一个，并产生具有所选相位偏移的检测输出。 定时误差计算电路可用于至少部分地基于所选择的相位偏移来计算模数转换器电路的定时误差。

    Array-reader based magnetic recording systems with frequency division multiplexing
    3.
    发明授权
    Array-reader based magnetic recording systems with frequency division multiplexing 有权
    基于阵列读取器的磁记录系统，具有频分复用

    公开(公告)号：US09129650B2

    公开(公告)日：2015-09-08

    申请号：US14021811

    申请日：2013-09-09

    Applicant: LSI Corporation

    Inventor： George Mathew ,  Bruce Wilson ,  Suharli Tedja ,  Eui Seok Hwang

    IPC: G11B20/06 ,  G11B5/09 ,  G11B5/035 ,  G11B5/02 ,  G11B20/10

    CPC classification number: G11B20/10268 ,  G11B20/10009 ,  G11B20/10046

    Abstract: A magnetic recording system includes an array of analog inputs operable to receive analog signals retrieved from a magnetic storage medium, a modulator operable to combine the analog signals to yield a frequency division multiplexed signal, a demodulator operable to yield a plurality of demodulated signals from the frequency division multiplexed signal corresponding to each channel of the array, and a joint equalizer operable to filter the plurality of demodulated signals to yield an equalized output.

    Abstract translation: 磁记录系统包括可操作以接收从磁存储介质检索的模拟信号的模拟输入阵列，可操作以组合模拟信号以产生频分多路复用信号的调制器，解调器，可操作以产生来自 对应于阵列的每个通道的频分多路复用信号，以及联合均衡器，可操作以对多个解调信号进行滤波以产生均衡的输出。

    Array-Reader Based Magnetic Recording Systems With Frequency Division Multiplexing
    4.
    发明申请
    Array-Reader Based Magnetic Recording Systems With Frequency Division Multiplexing 有权
    基于阵列读取器的磁记录系统具有频分复用

    公开(公告)号：US20150029608A1

    公开(公告)日：2015-01-29

    申请号：US14021811

    申请日：2013-09-09

    Applicant: LSI Corporation

    Inventor： George Mathew ,  Bruce Wilson ,  Suharli Tedja ,  Eui Seok Hwang

    IPC: G11B20/10

    CPC classification number: G11B20/10268 ,  G11B20/10009 ,  G11B20/10046

    Abstract: A magnetic recording system includes an array of analog inputs operable to receive analog signals retrieved from a magnetic storage medium, a modulator operable to combine the analog signals to yield a frequency division multiplexed signal, a demodulator operable to yield a plurality of demodulated signals from the frequency division multiplexed signal corresponding to each channel of the array, and a joint equalizer operable to filter the plurality of demodulated signals to yield an equalized output.

    Abstract translation: 磁记录系统包括可操作以接收从磁存储介质检索的模拟信号的模拟输入阵列，可操作以组合模拟信号以产生频分多路复用信号的调制器，解调器，可操作以产生来自 对应于阵列的每个通道的频分多路复用信号，以及联合均衡器，可操作以对多个解调信号进行滤波以产生均衡的输出。

    Timing Error Detector with Diversity Loop Detector Decision Feedback
    6.
    发明申请
    Timing Error Detector with Diversity Loop Detector Decision Feedback 有权
    具有分集环路检测器判定反馈的定时误差检测器

    公开(公告)号：US20140362463A1

    公开(公告)日：2014-12-11

    申请号：US13941464

    申请日：2013-07-13

    Applicant: LSI Corporation

    Inventor： Bruce Wilson ,  Yang Han ,  Yu Kou ,  Rui Cao

    IPC: G11B20/14 ,  G11B5/09

    CPC classification number: G11B5/09 ,  G11B20/10009 ,  G11B20/10046 ,  G11B20/10222 ,  G11B20/1403 ,  G11B2220/2516

    Abstract: Aspects of the disclosure pertain to an apparatus for detecting timing errors including an analog to digital converter circuit, a diversity loop detector and a timing error calculation circuit. The analog to digital converter circuit is operable to convert an input signal into a series of digital samples. The diversity loop detector is operable to apply a data detection algorithm to a plurality of signals derived from the series of digital samples at different phase offsets, to select one of the phase offsets, and to yield a detected output with the selected phase offset. The timing error calculation circuit is operable to calculate a timing error of the analog to digital converter circuit based at least in part on the selected phase offset.

    Abstract translation: 本公开的方面涉及用于检测定时误差的装置，包括模数转换器电路，分集环路检测器和定时误差计算电路。 模数转换器电路可操作以将输入信号转换为一系列数字采样。 分集环路检测器可操作以将数据检测算法应用于在不同相位偏移处从一系列数字样本导出的多个信号，以选择相位偏移中的一个，并产生具有所选相位偏移的检测输出。 定时误差计算电路可用于至少部分地基于所选择的相位偏移来计算模数转换器电路的定时误差。

    Data processing system with adjacent track interference metric
    8.
    发明授权
    Data processing system with adjacent track interference metric 有权
    具有相邻轨道干扰度量的数据处理系统

    公开(公告)号：US08861109B1

    公开(公告)日：2014-10-14

    申请号：US13963589

    申请日：2013-08-09

    Applicant: LSI Corporation

    Inventor： Eui Seok Hwang ,  Richard Rauschmayer ,  Shaohua Yang ,  Bruce Wilson

    IPC: G11B27/36

    CPC classification number: G11B5/02 ,  G11B20/10305 ,  G11B20/10472

    Abstract: A data processing circuit includes a long magnet identification circuit operable to identify long magnet bits in data to be processed, the long magnet bits comprising bits having a same value as a number of preceding and subsequent bits, an error calculation circuit operable to subtract an ideal version of the long magnet bits from the long magnet bits to yield an error signal, an adjacent track interference metric calculation circuit operable to calculate an adjacent track interference metric based on the error signal, and a comparator circuit operable to compare the adjacent track interference metric with a threshold value and to assert a refresh signal when the adjacent track interference metric is greater than the threshold value.

    Abstract translation: 数据处理电路包括：长磁体识别电路，用于识别要处理的数据中的长磁头位;所述长磁头位包括与前一位和后续位数相同值的位;误差计算电路，用于减去理想 版本的长磁头位产生误差信号，相邻轨道干扰度量计算电路，可操作以基于误差信号计算相邻轨道干扰度量;以及比较器电路，可操作以比较相邻轨道干扰度量 并且当相邻轨道干扰度量大于阈值时，断言刷新信号。

Patent Agency Ranking