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    Data-dependent equalizer circuit
    1.
    发明授权
    Data-dependent equalizer circuit 有权
    数据相关均衡电路

    公开(公告)号：US09252989B2

    公开(公告)日：2016-02-02

    申请号：US13628513

    申请日：2012-09-27

    Applicant: LSI Corporation

    Inventor： Jin Lu ,  Shaohua Yang ,  Weijun Tan

    IPC: H03D1/00 ,  H04L25/03

    CPC classification number: H04L25/03038

    Abstract: A data dependent equalizer circuit includes a plurality of noise prediction filters. Respective ones of the noise prediction filters are configured to filter noise in sample data for at least one predetermined non-return to zero (NRZ) condition. A plurality of equalizers is communicatively coupled with the plurality of noise prediction filters. Respective ones of the plurality of equalizers are configured to yield equalized sample data that corresponds to the at least one predetermined NRZ condition for one or more of the noise prediction filters.

    Abstract translation: 数据相关均衡器电路包括多个噪声预测滤波器。 各个噪声预测滤波器被配置为在至少一个预定的不归零（NRZ）条件下滤波采样数据中的噪声。 多个均衡器与多个噪声预测滤波器通信耦合。 多个均衡器中的各个均衡器被配置为产生对应于一个或多个噪声预测滤波器的至少一个预定NRZ条件的均衡样本数据。

    PROGRAMMABLE QUASI-CYCLIC LOW-DENSITY PARITY CHECK (QC LDPC) ENCODER FOR READ CHANNEL
    5.
    发明申请
    PROGRAMMABLE QUASI-CYCLIC LOW-DENSITY PARITY CHECK (QC LDPC) ENCODER FOR READ CHANNEL 有权
    可编程循环低密度奇偶校验（QC LDPC）编解码器

    公开(公告)号：US20130091403A1

    公开(公告)日：2013-04-11

    申请号：US13632768

    申请日：2012-10-01

    Applicant: LSI Corporation

    Inventor： Shaohua Yang ,  Changyou Xu ,  Richard Rauschmayer ,  Hao Zhong ,  Weijun Tan

    IPC: H03M13/05

    CPC classification number: H03M13/05 ,  G06F11/1008 ,  H03M13/116 ,  H03M13/2792

    Abstract: The present invention is a programmable QC LDPC encoder for encoding user data. The encoder may be configurable for implementation with a read channel. The encoder may include a plurality of barrel shifter circuits. The barrel shifter circuits are configured for generating a plurality of parity bits based on interleaved user bits received by the encoder. The barrel shifter circuits are further configured for outputting the parity bits. The encoder may further include an encoder interleaver memory. The encoder interleaver memory may be communicatively coupled with the barrel shifter circuits and may receive the parity bits output from the barrel shifter circuits. The encoder interleaver may be configured for interleaving the parity bits. Further, the encoder may be configured for outputting the interleaved parity bits to a multiplexer. The barrel shifter circuits may generate the plurality of parity bits via an encoding algorithm: p=u*GT.

    Abstract translation: 本发明是用于编码用户数据的可编程QC LDPC编码器。 编码器可以被配置为用读通道实现。 编码器可以包括多个桶形移位器电路。 桶形移位器电路被配置为基于由编码器接收的交织的用户比特生成多个奇偶校验位。 桶形移位器电路还被配置为输出奇偶校验位。 编码器还可以包括编码器交织器存储器。 编码器交织器存储器可以与桶形移位器电路通信耦合，并且可以接收从桶形移位器电路输出的奇偶校验位。 编码器交织器可以被配置为交织奇偶校验位。 此外，编码器可以被配置为将交错的奇偶校验位输出到多路复用器。 桶形移位器电路可以通过编码算法生成多个奇偶校验位：p = u * GT。

    Gated noise-predictive filter calibration
    6.
    发明授权
    Gated noise-predictive filter calibration 有权
    门控噪声预测滤波器校准

    公开(公告)号：US09202514B1

    公开(公告)日：2015-12-01

    申请号：US14334410

    申请日：2014-07-17

    Applicant: LSI Corporation

    Inventor： Jianzhong Huang ,  Shaohua Yang ,  Haitao Xia ,  Fuminori Sai ,  Weijun Tan

    IPC: G11B5/09 ,  G11B5/035 ,  G11B20/10

    CPC classification number: G11B20/10046

    Abstract: An apparatus for calibrating a noise predictive filter includes a noise-predictive filter operable to filter digital data samples to yield filtered data samples, a calibration circuit operable to calculate tap coefficients for the noise-predictive filter based at least in part on the digital data samples, and a gating circuit operable to select a portion of the digital data samples for use by the calibration circuit in calculating the tap coefficients.

    Abstract translation: 用于校准噪声预测滤波器的装置包括噪声预测滤波器，其可操作以对数字数据样本进行滤波以产生经滤波的数据采样;校准电路，可用于至少部分地基于数字数据样本来计算噪声预测滤波器的抽头系数 以及门控电路，其可操作以选择数字数据样本的一部分，以供校准电路在计算抽头系数时使用。

    Programmable quasi-cyclic low-density parity check (QC LDPC) encoder for read channel
    7.
    发明授权
    Programmable quasi-cyclic low-density parity check (QC LDPC) encoder for read channel 有权
    用于读通道的可编程准循环低密度奇偶校验（QC LDPC）编码器

    公开(公告)号：US09166622B2

    公开(公告)日：2015-10-20

    申请号：US13632768

    申请日：2012-10-01

    Applicant: LSI Corporation

    Inventor： Shaohua Yang ,  Changyou Xu ,  Richard Rauschmayer ,  Hao Zhong ,  Weijun Tan

    IPC: H03M13/00 ,  H03M13/05 ,  H03M13/11 ,  G06F11/10 ,  H03M13/27

    CPC classification number: H03M13/05 ,  G06F11/1008 ,  H03M13/116 ,  H03M13/2792

    Abstract: The present invention is a programmable QC LDPC encoder for encoding user data. The encoder may be configurable for implementation with a read channel. The encoder may include a plurality of barrel shifter circuits. The barrel shifter circuits are configured for generating a plurality of parity bits based on interleaved user bits received by the encoder. The barrel shifter circuits are further configured for outputting the parity bits. The encoder may further include an encoder interleaver memory. The encoder interleaver memory may be communicatively coupled with the barrel shifter circuits and may receive the parity bits output from the barrel shifter circuits. The encoder interleaver may be configured for interleaving the parity bits. Further, the encoder may be configured for outputting the interleaved parity bits to a multiplexer. The barrel shifter circuits may generate the plurality of parity bits via an encoding algorithm: p=u*GT.

    Abstract translation: 本发明是用于编码用户数据的可编程QC LDPC编码器。 编码器可以被配置为用读通道实现。 编码器可以包括多个桶形移位器电路。 桶形移位器电路被配置为基于由编码器接收的交织的用户比特生成多个奇偶校验位。 桶形移位器电路还被配置为输出奇偶校验位。 编码器还可以包括编码器交织器存储器。 编码器交织器存储器可以与桶形移位器电路通信耦合，并且可以接收从桶形移位器电路输出的奇偶校验位。 编码器交织器可以被配置为交织奇偶校验位。 此外，编码器可以被配置为将交错的奇偶校验位输出到多路复用器。 桶形移位器电路可以通过编码算法生成多个奇偶校验位：p = u * GT。

    Equalization combining outputs of multiple component filters
    8.
    发明授权
    Equalization combining outputs of multiple component filters 有权
    均衡组合多个组件滤波器的输出

    公开(公告)号：US08810949B2

    公开(公告)日：2014-08-19

    申请号：US13724962

    申请日：2012-12-21

    Applicant: LSI Corporation

    Inventor： Jin Lu ,  Weijun Tan ,  Shaohua Yang

    IPC: G11B5/09 ,  G11B20/10 ,  G11B5/035

    CPC classification number: G11B20/10287 ,  G11B20/10046

    Abstract: An apparatus comprises read channel circuitry and associated signal processing circuitry. The signal processing circuitry comprises: an equalizer configured to combine an output of two or more component filters into a single equalized data signal; a detector with an input coupled to an output of the equalizer configured to determine a set of soft outputs, hard decision information and reliability indicators of the single equalized data signal; a decoder with an input coupled to an output of the decoder configured to perform an iterative decoding process using the set of soft outputs, hard decision information and reliability indicators to determine a decoded data signal; and a multiplexer with a first input coupled to an output of the decoder, a second input coupled to an output of the detector, and an output coupled to an input of the equalizer. The hard decision information is used to train the equalizer.

    Abstract translation: 一种装置包括读通道电路和相关的信号处理电路。 信号处理电路包括：均衡器，被配置为将两个或更多个分量滤波器的输出组合成单个均衡数据信号; 具有耦合到所述均衡器的输出的输入的检测器，被配置为确定所述单个均衡数据信号的一组软输出，硬判决信息和可靠性指示符; 解码器，具有耦合到所述解码器的输出的输入，所述输出被配置为使用所述一组软输出执行迭代解码处理，硬判决信息和可靠性指示符，以确定解码的数据信号; 以及多路复用器，其具有耦合到解码器的输出的第一输入，耦合到检测器的输出的第二输入和耦合到均衡器的输入的输出。 硬判决信息用于训练均衡器。

    READ CHANNEL ERROR CORRECTION USING MULTIPLE CALIBRATORS
    9.
    发明申请
    READ CHANNEL ERROR CORRECTION USING MULTIPLE CALIBRATORS 有权

    公开(公告)号：US20140139943A1

    公开(公告)日：2014-05-22

    申请号：US13681917

    申请日：2012-11-20

    Applicant: LSI CORPORATION

    Inventor： Weijun Tan ,  Shaohua Yang

    IPC: G11B20/18

    CPC classification number: G11B20/18 ,  G11B20/10046 ,  G11B20/1816 ,  G11B20/1833 ,  G11B2020/185

    Abstract: Read channel circuitry comprises a decoder and error correction circuitry. The error correction circuitry is configured to calibrate a first set of filters using a read channel data signal, to determine first hard decision information regarding the read channel data signal using the calibrated first set of filters, to determine an error corrected read channel data signal using the first hard decision information, to calibrate a second set of filters using the error corrected read channel data signal, to determine second hard decision information regarding the error corrected read channel data signal using the calibrated second set of filters, and to decode the second hard decision information. The first set of filters and the second set of filters are calibrated in respective first and second calibrators.

    Systems and methods for floating variance branch metric calculation
    10.
    发明授权
    Systems and methods for floating variance branch metric calculation 有权
    用于浮动方差分支度量计算的系统和方法

    公开(公告)号：US09324363B2

    公开(公告)日：2016-04-26

    申请号：US13945216

    申请日：2013-07-18

    Applicant: LSI Corporation

    Inventor： Weijun Tan ,  Shaohua Yang ,  Xuebin Wu

    IPC: G11B5/09 ,  G11B20/10

    CPC classification number: G11B20/10046 ,  G11B20/10268

    Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for data detection. As one example, a data processing system is described that includes a variance calculation circuit operable to calculate a variance of a data input; and a branch metric calculation circuit operable to calculate a branch metric based at least in part on the variance.

    Abstract translation: 本发明涉及用于数据处理的系统和方法，更具体地涉及用于数据检测的系统和方法。 作为一个示例，描述了包括可操作以计算数据输入的方差的方差计算电路的数据处理系统; 以及分支度量计算电路，其可操作以至少部分地基于所述方差来计算分支度量。

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