公开(公告)号：US20050215022A1

公开(公告)日：2005-09-29

申请号：US10810419

申请日：2004-03-26

申请人： Lahir Adam ,  Eddie Breashears ,  Alwin Tsao

发明人： Lahir Adam ,  Eddie Breashears ,  Alwin Tsao

IPC分类号： H01L21/28 ,  H01L21/331 ,  H01L21/8234 ,  H01L29/78

CPC分类号： H01L21/823462 ,  H01L21/2822 ,  H01L29/7833

摘要： The present invention provides a tri-gate lower power device and method for fabricating that tri-gate semiconductor device. The tri-gate device includes a first gate [455] located over a high voltage gate dielectric [465] within a high voltage region [460], a second gate [435] located over a low voltage gate dielectric [445] within a low voltage core region [440] and a third gate [475] located over an intermediate core oxide [485] within an intermediate core region [480]. One method of fabrication includes forming a high voltage gate dielectric layer [465] over a semiconductor substrate [415], implanting a low dose of nitrogen [415a] into the semiconductor substrate [415] in a low voltage core region [440], and forming a core gate dielectric layer [445] over the low voltage core region [440], including forming an intermediate core gate dielectric layer [485] over an intermediate core region [480].

摘要翻译： 本发明提供一种用于制造三栅极半导体器件的三栅极低功率器件和方法。 三栅极器件包括位于高电压区域[460]内的高压栅极电介质[465]上的第一栅极[455]，位于低电压栅极电介质[450]内的第二栅极[435] 电压芯区域[440]和位于中间核心区域[480]内的第三栅极[475]。 一种制造方法包括在半导体衬底[415]上形成高电压栅介质层，在低电压核心区域[440]中将低剂量的氮[415a]注入到半导体衬底[415]中， 以及在所述低压芯区域[440]上形成核心栅介质层，包括在中间核心区域[480]上形成中间核心栅介质层[485]。

公开(公告)号：US20050227439A1

公开(公告)日：2005-10-13

申请号：US11144202

申请日：2005-06-02

申请人： Lahir Adam ,  Eddie Breashears ,  Alwin Tsao

发明人： Lahir Adam ,  Eddie Breashears ,  Alwin Tsao

IPC分类号： H01L21/28 ,  H01L21/331 ,  H01L21/8234 ,  H01L29/78

CPC分类号： H01L21/823462 ,  H01L21/2822 ,  H01L29/7833

摘要： The present invention provides a tri-gate lower power device and method for fabricating that tri-gate semiconductor device. The tri-gate device includes a first gate [455] located over a high voltage gate dielectric [465] within a high voltage region [460], a second gate [435] located over a low voltage gate dielectric [445] within a low voltage core region [440] and a third gate [475] located over an intermediate core oxide [485] within an intermediate core region [480]. One method of fabrication includes forming a high voltage gate dielectric layer [465] over a semiconductor substrate [415], implanting a low dose of nitrogen [415a] into the semiconductor substrate [415] in a low voltage core region [440], and forming a core gate dielectric layer [445] over the low voltage core region [440], including forming an intermediate core gate dielectric layer [485] over an intermediate core region [480].

摘要翻译： 本发明提供一种用于制造三栅极半导体器件的三栅极低功率器件和方法。 三栅极器件包括位于高电压区域[460]内的高压栅极电介质[465]上的第一栅极[455]，位于低电压栅极电介质[450]内的第二栅极[435] 电压芯区域[440]和位于中间核心区域[480]内的第三栅极[475]。 一种制造方法包括在半导体衬底[415]上形成高电压栅介质层，在低电压核心区域[440]中将低剂量的氮[415a]注入到半导体衬底[415]中， 以及在所述低压芯区域[440]上形成核心栅介质层，包括在中间核心区域[480]上形成中间核心栅介质层[485]。

公开(公告)号：US20050156286A1

公开(公告)日：2005-07-21

申请号：US11038545

申请日：2005-01-18

申请人： Brian Kirkpatrick ,  Mercer Brugler ,  Eddie Breashears ,  Jon Holt ,  Corbett Zabierek ,  Rajesh Khamankar

发明人： Brian Kirkpatrick ,  Mercer Brugler ,  Eddie Breashears ,  Jon Holt ,  Corbett Zabierek ,  Rajesh Khamankar

IPC分类号： H01L21/28 ,  H01L21/3105 ,  H01L29/51 ,  H01L21/26 ,  H01L21/324 ,  H01L21/42 ,  H01L21/4763 ,  H01L21/477 ,  H01L23/58

CPC分类号： H01L21/28176 ,  H01L21/3105 ,  H01L29/518

摘要： The present invention provides a method for improving a physical property of a substrate, a method for manufacturing an integrated circuit, and an integrated circuit manufactured using the aforementioned method. In one aspect of the invention, the method for improving a physical property of a substrate includes subjecting the substrate to effects of a plasma process 830, wherein the substrate has a physical property defect value associated therewith subsequent to the plasma process. The method further includes exposing the substrate to an ultraviolet (UV) energy source 840 to improve the physical property defect value.

摘要翻译： 本发明提供一种提高基板的物理性能的方法，集成电路的制造方法以及使用上述方法制造的集成电路。 在本发明的一个方面，用于改善基板的物理性能的方法包括使基板受到等离子体工艺830的影响，其中基板在等离子体处理之后具有与其相关联的物理性能缺陷值。 该方法还包括将衬底暴露于紫外（UV）能量源840以改善物理性能缺陷值。

公开(公告)号：US06869862B2

公开(公告)日：2005-03-22

申请号：US10637288

申请日：2003-08-08

申请人： Brian K. Kirkpatrick ,  Mercer Brugler ,  Eddie Breashears ,  Jon Holt ,  Corbett Zabierek ,  Rajesh Khamankar

发明人： Brian K. Kirkpatrick ,  Mercer Brugler ,  Eddie Breashears ,  Jon Holt ,  Corbett Zabierek ,  Rajesh Khamankar

IPC分类号： H01L21/28 ,  H01L21/3105 ,  H01L29/51 ,  H01I21/46 ,  H01L21/479 ,  H01I21/326 ,  H01I21/78

CPC分类号： H01L21/28176 ,  H01L21/3105 ,  H01L29/518

摘要： The present invention provides a method for improving a physical property of a substrate, a method for manufacturing an integrated circuit, and an integrated circuit manufactured using the aforementioned method. In one aspect of the invention, the method for improving a physical property of a substrate includes subjecting the substrate to effects of a plasma process 830, wherein the substrate has a physical property defect value associated therewith subsequent to the plasma process. The method further includes exposing the substrate to an ultraviolet (UV) energy source 840 to improve the physical property defect value.

摘要翻译： 本发明提供一种提高基板的物理性能的方法，集成电路的制造方法以及使用上述方法制造的集成电路。 在本发明的一个方面，用于改善基板的物理性能的方法包括使基板受到等离子体工艺830的影响，其中基板在等离子体处理之后具有与其相关联的物理性能缺陷值。 该方法还包括将衬底暴露于紫外（UV）能量源840以改善物理性能缺陷值。