公开(公告)号：US20050215022A1

公开(公告)日：2005-09-29

申请号：US10810419

申请日：2004-03-26

申请人： Lahir Adam ,  Eddie Breashears ,  Alwin Tsao

发明人： Lahir Adam ,  Eddie Breashears ,  Alwin Tsao

IPC分类号： H01L21/28 ,  H01L21/331 ,  H01L21/8234 ,  H01L29/78

CPC分类号： H01L21/823462 ,  H01L21/2822 ,  H01L29/7833

摘要： The present invention provides a tri-gate lower power device and method for fabricating that tri-gate semiconductor device. The tri-gate device includes a first gate [455] located over a high voltage gate dielectric [465] within a high voltage region [460], a second gate [435] located over a low voltage gate dielectric [445] within a low voltage core region [440] and a third gate [475] located over an intermediate core oxide [485] within an intermediate core region [480]. One method of fabrication includes forming a high voltage gate dielectric layer [465] over a semiconductor substrate [415], implanting a low dose of nitrogen [415a] into the semiconductor substrate [415] in a low voltage core region [440], and forming a core gate dielectric layer [445] over the low voltage core region [440], including forming an intermediate core gate dielectric layer [485] over an intermediate core region [480].

摘要翻译： 本发明提供一种用于制造三栅极半导体器件的三栅极低功率器件和方法。 三栅极器件包括位于高电压区域[460]内的高压栅极电介质[465]上的第一栅极[455]，位于低电压栅极电介质[450]内的第二栅极[435] 电压芯区域[440]和位于中间核心区域[480]内的第三栅极[475]。 一种制造方法包括在半导体衬底[415]上形成高电压栅介质层，在低电压核心区域[440]中将低剂量的氮[415a]注入到半导体衬底[415]中， 以及在所述低压芯区域[440]上形成核心栅介质层，包括在中间核心区域[480]上形成中间核心栅介质层[485]。

公开(公告)号：US20050227439A1

公开(公告)日：2005-10-13

申请号：US11144202

申请日：2005-06-02

申请人： Lahir Adam ,  Eddie Breashears ,  Alwin Tsao

发明人： Lahir Adam ,  Eddie Breashears ,  Alwin Tsao

IPC分类号： H01L21/28 ,  H01L21/331 ,  H01L21/8234 ,  H01L29/78

CPC分类号： H01L21/823462 ,  H01L21/2822 ,  H01L29/7833

摘要： The present invention provides a tri-gate lower power device and method for fabricating that tri-gate semiconductor device. The tri-gate device includes a first gate [455] located over a high voltage gate dielectric [465] within a high voltage region [460], a second gate [435] located over a low voltage gate dielectric [445] within a low voltage core region [440] and a third gate [475] located over an intermediate core oxide [485] within an intermediate core region [480]. One method of fabrication includes forming a high voltage gate dielectric layer [465] over a semiconductor substrate [415], implanting a low dose of nitrogen [415a] into the semiconductor substrate [415] in a low voltage core region [440], and forming a core gate dielectric layer [445] over the low voltage core region [440], including forming an intermediate core gate dielectric layer [485] over an intermediate core region [480].

摘要翻译： 本发明提供一种用于制造三栅极半导体器件的三栅极低功率器件和方法。 三栅极器件包括位于高电压区域[460]内的高压栅极电介质[465]上的第一栅极[455]，位于低电压栅极电介质[450]内的第二栅极[435] 电压芯区域[440]和位于中间核心区域[480]内的第三栅极[475]。 一种制造方法包括在半导体衬底[415]上形成高电压栅介质层，在低电压核心区域[440]中将低剂量的氮[415a]注入到半导体衬底[415]中， 以及在所述低压芯区域[440]上形成核心栅介质层，包括在中间核心区域[480]上形成中间核心栅介质层[485]。

公开(公告)号：US08067279B2

公开(公告)日：2011-11-29

申请号：US12489223

申请日：2009-06-22

申请人： Kayvan Sadra ,  Alwin Tsao ,  Seetharaman Sridhar ,  Amitava Chatterjee

发明人： Kayvan Sadra ,  Alwin Tsao ,  Seetharaman Sridhar ,  Amitava Chatterjee

IPC分类号： H01L21/00

CPC分类号： H01L21/823807 ,  H01L21/76229 ,  H01L21/76237 ,  H01L21/823481 ,  H01L21/823493 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/1052

摘要： The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and other logic portions of a device. The isolation mechanism of the embedded memory portion is improved relative to other portions of the device by increasing dopant concentrations or reducing the depth of the dopant profiles within well regions of the embedded memory array. As a result, smaller isolation spacing can be employed thereby permitting a more compact array. The isolation mechanism of the logic portion is relatively less than that of the embedded memory portion, which permits greater operational speed for the logic.

摘要翻译： 本发明通过提供用于在嵌入式存储器和设备的其他逻辑部分中利用不同隔离方案的机制来促进半导体器件制造。 嵌入式存储器部分的隔离机构相对于器件的其它部分通过增加掺杂剂浓度或降低嵌入式存储器阵列的阱区域内的掺杂剂分布的深度来改进。 因此，可以采用更小的隔离间隔，从而允许更紧凑的阵列。 逻辑部分的隔离机制相对小于嵌入式存储器部分的隔离机制，这允许逻辑的更高的操作速度。

公开(公告)号：US20060024899A1

公开(公告)日：2006-02-02

申请号：US10909648

申请日：2004-07-31

申请人： Darius Crenshaw ,  Byron Williams ,  Alwin Tsao ,  Hisashi Shichijo ,  Satyavolu Papa Rao ,  Kenneth Brennan ,  Steven Lytle

发明人： Darius Crenshaw ,  Byron Williams ,  Alwin Tsao ,  Hisashi Shichijo ,  Satyavolu Papa Rao ,  Kenneth Brennan ,  Steven Lytle

IPC分类号： H01L21/8242 ,  H01L21/20

CPC分类号： H01L23/5223 ,  H01L21/76834 ,  H01L28/57 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method (10) of forming a MIM (metal insulator metal) capacitor is disclosed whereby adverse affects associated with copper diffusion are mitigated even as the capacitor is scaled down. A sidewall spacer (156) is formed against an edge (137) of a layer of bottom electrode/copper diffusion barrier material (136), an edge (151) of a layer of capacitor dielectric material (150) and at least some of an edge (153) of a layer of top electrode material. The sidewall spacer (156) is dielectric or non-conductive and mitigates “shorting” currents that can develop between the plates as a result of copper diffusion. Bottom electrode diffusion barrier material (136) mitigates copper diffusion and/or copper drift, thereby reducing the likelihood of premature device failure.

摘要翻译： 公开了形成MIM（金属绝缘金属）电容器的方法（10），其中即使电容器按比例缩小，也减轻了与铜扩散相关的不利影响。 侧壁间隔物（156）抵靠着底部电极/铜扩散阻挡材料层（136）的边缘（137），电容器介电材料层（150）的边缘（151）和至少一些 边缘（153）的顶层电极材料层。 侧壁间隔物（156）是电介质或非导电的，并且减轻由于铜扩散而在板之间产生的“短路”电流。 底部电极扩散阻挡材料（136）减轻了铜扩散和/或铜漂移，从而降低了设备过早失效的可能性。

公开(公告)号：US20090258471A1

公开(公告)日：2009-10-15

申请号：US12489223

申请日：2009-06-22

申请人： Kayvan Sadra ,  Alwin Tsao ,  Seetharaman Sridhar ,  Amitava Chatterjee

发明人： Kayvan Sadra ,  Alwin Tsao ,  Seetharaman Sridhar ,  Amitava Chatterjee

IPC分类号： H01L21/8244 ,  H01L21/762

CPC分类号： H01L21/823807 ,  H01L21/76229 ,  H01L21/76237 ,  H01L21/823481 ,  H01L21/823493 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/1052

摘要： The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and other logic portions of a device. The isolation mechanism of the embedded memory portion is improved relative to other portions of the device by increasing dopant concentrations or reducing the depth of the dopant profiles within well regions of the embedded memory array. As a result, smaller isolation spacing can be employed thereby permitting a more compact array. The isolation mechanism of the logic portion is relatively less than that of the embedded memory portion, which permits greater operational speed for the logic.

摘要翻译： 本发明通过提供用于在嵌入式存储器和设备的其他逻辑部分中利用不同隔离方案的机制来促进半导体器件制造。 嵌入式存储器部分的隔离机构相对于器件的其它部分通过增加掺杂剂浓度或降低嵌入式存储器阵列的阱区域内的掺杂剂分布的深度来改进。 因此，可以采用更小的隔离间隔，从而允许更紧凑的阵列。 逻辑部分的隔离机制相对小于嵌入式存储器部分的隔离机制，这允许逻辑的更高的操作速度。

公开(公告)号：US07193277B2

公开(公告)日：2007-03-20

申请号：US11054083

申请日：2005-02-08

申请人： Kayvan Sadra ,  Alwin Tsao ,  Seetharaman Sridhar ,  Amitava Chatterjee

发明人： Kayvan Sadra ,  Alwin Tsao ,  Seetharaman Sridhar ,  Amitava Chatterjee

IPC分类号： H01L21/44

CPC分类号： H01L21/823807 ,  H01L21/76229 ,  H01L21/76237 ,  H01L21/823481 ,  H01L21/823493 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/1052

摘要： The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and other logic portions of a device. The isolation mechanism of the embedded memory portion is improved relative to other portions of the device by increasing dopant concentrations or reducing the depth of the dopant profiles within well regions of the embedded memory array. As a result, smaller isolation spacing can be employed thereby permitting a more compact array. The isolation mechanism of the logic portion is relatively less than that of the embedded memory portion, which permits greater operational speed for the logic.

摘要翻译： 本发明通过提供用于在嵌入式存储器和设备的其他逻辑部分中利用不同隔离方案的机制来促进半导体器件制造。 嵌入式存储器部分的隔离机构相对于器件的其它部分通过增加掺杂剂浓度或降低嵌入式存储器阵列的阱区域内的掺杂剂分布的深度来改进。 因此，可以采用更小的隔离间隔，从而允许更紧凑的阵列。 逻辑部分的隔离机制相对小于嵌入式存储器部分的隔离机制，这允许逻辑的更高的操作速度。

公开(公告)号：US20060084230A1

公开(公告)日：2006-04-20

申请号：US11296164

申请日：2005-12-07

申请人： Kayvan Sadra ,  Alwin Tsao ,  Seetharaman Sridhar ,  Amitava Chatterjee

发明人： Kayvan Sadra ,  Alwin Tsao ,  Seetharaman Sridhar ,  Amitava Chatterjee

IPC分类号： H01L21/8234

CPC分类号： H01L21/823807 ,  H01L21/76229 ,  H01L21/76237 ,  H01L21/823481 ,  H01L21/823493 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/1052

摘要： The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and other logic portions of a device. The isolation mechanism of the embedded memory portion is improved relative to other portions of the device by increasing dopant concentrations or reducing the depth of the dopant profiles within well regions of the embedded memory array. As a result, smaller isolation spacing can be employed thereby permitting a more compact array. The isolation mechanism of the logic portion is relatively less than that of the embedded memory portion, which permits greater operational speed for the logic.

公开(公告)号：US07314800B2

公开(公告)日：2008-01-01

申请号：US11296164

申请日：2005-12-07

申请人： Kayvan Sadra ,  Alwin Tsao ,  Seetharaman Sridhar ,  Amitava Chatterjee

发明人： Kayvan Sadra ,  Alwin Tsao ,  Seetharaman Sridhar ,  Amitava Chatterjee

IPC分类号： H01L21/00

CPC分类号： H01L21/823807 ,  H01L21/76229 ,  H01L21/76237 ,  H01L21/823481 ,  H01L21/823493 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/1052

摘要： The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and other logic portions of a device. The isolation mechanism of the embedded memory portion is improved relative to other portions of the device by increasing dopant concentrations or reducing the depth of the dopant profiles within well regions of the embedded memory array. As a result, smaller isolation spacing can be employed thereby permitting a more compact array. The isolation mechanism of the logic portion is relatively less than that of the embedded memory portion, which permits greater operational speed for the logic.

摘要翻译： 本发明通过提供用于在嵌入式存储器和设备的其他逻辑部分中利用不同隔离方案的机制来促进半导体器件制造。 嵌入式存储器部分的隔离机构相对于器件的其它部分通过增加掺杂剂浓度或降低嵌入式存储器阵列的阱区域内的掺杂剂分布的深度来改进。 因此，可以采用更小的隔离间隔，从而允许更紧凑的阵列。 逻辑部分的隔离机制相对小于嵌入式存储器部分的隔离机制，这允许逻辑的更高的操作速度。

公开(公告)号：US20070166906A1

公开(公告)日：2007-07-19

申请号：US11683721

申请日：2007-03-08

申请人： Majid Mansoori ,  Alwin Tsao ,  Antonio Pacheco Rotondaro ,  Brian Smith

发明人： Majid Mansoori ,  Alwin Tsao ,  Antonio Pacheco Rotondaro ,  Brian Smith

IPC分类号： H01L21/8238

CPC分类号： H01L21/26506 ,  H01L21/28044 ,  H01L21/28114 ,  H01L21/32137 ,  H01L29/42376

摘要： The present invention pertains to formation of a transistor in a manner that mitigates overlap capacitances, thereby facilitating, among other things, enhanced switching speeds. More particularly, a gate stack of the transistor is formed to include an optional layer of poly-SiGe and a layer of poly-Si, where at least one or the layers comprises carbon. The stack may also include a polysilicon seed layer that can also comprise carbon. The carbon changes the components of sidewall passivation materials and affects etch rates during an etching process, thereby facilitating isotropic etching. The changed passivation materials coupled with an enhanced sensitivity of the poly-SiGe and carbon-doped poly-SiGe layer to an etchant utilized in the etching process causes the stack to have a notched appearance. The tapered configuration of the gate stack provides little, if any, area for dopants that may migrate under the gate structure to overlap the conductive layers in the stack, and thus mitigates the opportunity for overlap capacitances to arise.

摘要翻译： 本发明涉及以减轻重叠电容的方式形成晶体管，从而有利于提高切换速度。 更具体地，晶体管的栅极堆叠形成为包括任选的多晶硅层和多晶硅层，其中至少一个或多个层包含碳。 堆叠还可以包括也可以包含碳的多晶硅种子层。 碳改变侧壁钝化材料的组分并影响蚀刻过程中的蚀刻速率，从而促进各向同性蚀刻。 与蚀刻过程中使用的蚀刻剂相比，改变的钝化材料与多晶硅和掺杂碳的多晶硅层的增强灵敏度相结合，使堆叠具有缺口外观。 栅极堆叠的锥形配置对于可能在栅极结构下迁移以与堆叠中的导电层重叠的掺杂剂提供很小的（如果有的话）区域，并且因此减轻了重叠电容出现的机会。

公开(公告)号：US20060024910A1

公开(公告)日：2006-02-02

申请号：US10899664

申请日：2004-07-27

申请人： Amitava Chatterjee ,  Alwin Tsao ,  Manuel Quevedo-Lopez ,  Jong Yoon ,  Shaoping Tang

发明人： Amitava Chatterjee ,  Alwin Tsao ,  Manuel Quevedo-Lopez ,  Jong Yoon ,  Shaoping Tang

IPC分类号： H01L21/76

CPC分类号： H01L21/76237 ,  H01L21/823878

摘要： A method (200) of forming an isolation structure is disclosed, and includes forming an isolation trench in a semiconductor body (214) associated with an isolation region, and filling a bottom portion of the isolation trench with an implant masking material (216). An angled ion implant is performed into the isolation trench (218) after having the bottom portion thereof filled with the implant masking material, thereby forming a threshold voltage compensation region in the semiconductor body. Subsequently, the isolation trench is filled with a dielectric material (220).

摘要翻译： 公开了一种形成隔离结构的方法（200），并且包括在与隔离区域相关联的半导体本体（214）中形成隔离沟槽，并用植入物掩模材料（216）填充隔离沟槽的底部。 在其底部填充有注入掩模材料之后，在隔离沟槽（218）中进行成角度的离子注入，从而在半导体本体中形成阈值电压补偿区域。 随后，隔离沟槽填充有电介质材料（220）。