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    Tri-gate low power device and method for manufacturing the same
    1.
    发明申请
    Tri-gate low power device and method for manufacturing the same 有权
    三栅低功率器件及其制造方法

    公开(公告)号：US20050215022A1

    公开(公告)日：2005-09-29

    申请号：US10810419

    申请日：2004-03-26

    申请人： Lahir Adam ,  Eddie Breashears ,  Alwin Tsao

    发明人： Lahir Adam ,  Eddie Breashears ,  Alwin Tsao

    IPC分类号： H01L21/28 ,  H01L21/331 ,  H01L21/8234 ,  H01L29/78

    CPC分类号： H01L21/823462 ,  H01L21/2822 ,  H01L29/7833

    摘要： The present invention provides a tri-gate lower power device and method for fabricating that tri-gate semiconductor device. The tri-gate device includes a first gate [455] located over a high voltage gate dielectric [465] within a high voltage region [460], a second gate [435] located over a low voltage gate dielectric [445] within a low voltage core region [440] and a third gate [475] located over an intermediate core oxide [485] within an intermediate core region [480]. One method of fabrication includes forming a high voltage gate dielectric layer [465] over a semiconductor substrate [415], implanting a low dose of nitrogen [415a] into the semiconductor substrate [415] in a low voltage core region [440], and forming a core gate dielectric layer [445] over the low voltage core region [440], including forming an intermediate core gate dielectric layer [485] over an intermediate core region [480].

    摘要翻译： 本发明提供一种用于制造三栅极半导体器件的三栅极低功率器件和方法。 三栅极器件包括位于高电压区域[460]内的高压栅极电介质[465]上的第一栅极[455]，位于低电压栅极电介质[450]内的第二栅极[435] 电压芯区域[440]和位于中间核心区域[480]内的第三栅极[475]。 一种制造方法包括在半导体衬底[415]上形成高电压栅介质层，在低电压核心区域[440]中将低剂量的氮[415a]注入到半导体衬底[415]中， 以及在所述低压芯区域[440]上形成核心栅介质层，包括在中间核心区域[480]上形成中间核心栅介质层[485]。

    Tri-gate low power device and method for manufacturing the same
    2.
    发明申请
    Tri-gate low power device and method for manufacturing the same 有权
    三栅低功率器件及其制造方法

    公开(公告)号：US20050227439A1

    公开(公告)日：2005-10-13

    申请号：US11144202

    申请日：2005-06-02

    申请人： Lahir Adam ,  Eddie Breashears ,  Alwin Tsao

    发明人： Lahir Adam ,  Eddie Breashears ,  Alwin Tsao

    IPC分类号： H01L21/28 ,  H01L21/331 ,  H01L21/8234 ,  H01L29/78

    CPC分类号： H01L21/823462 ,  H01L21/2822 ,  H01L29/7833

    摘要： The present invention provides a tri-gate lower power device and method for fabricating that tri-gate semiconductor device. The tri-gate device includes a first gate [455] located over a high voltage gate dielectric [465] within a high voltage region [460], a second gate [435] located over a low voltage gate dielectric [445] within a low voltage core region [440] and a third gate [475] located over an intermediate core oxide [485] within an intermediate core region [480]. One method of fabrication includes forming a high voltage gate dielectric layer [465] over a semiconductor substrate [415], implanting a low dose of nitrogen [415a] into the semiconductor substrate [415] in a low voltage core region [440], and forming a core gate dielectric layer [445] over the low voltage core region [440], including forming an intermediate core gate dielectric layer [485] over an intermediate core region [480].

    摘要翻译： 本发明提供一种用于制造三栅极半导体器件的三栅极低功率器件和方法。 三栅极器件包括位于高电压区域[460]内的高压栅极电介质[465]上的第一栅极[455]，位于低电压栅极电介质[450]内的第二栅极[435] 电压芯区域[440]和位于中间核心区域[480]内的第三栅极[475]。 一种制造方法包括在半导体衬底[415]上形成高电压栅介质层，在低电压核心区域[440]中将低剂量的氮[415a]注入到半导体衬底[415]中， 以及在所述低压芯区域[440]上形成核心栅介质层，包括在中间核心区域[480]上形成中间核心栅介质层[485]。

    Method to strain NMOS devices while mitigating dopant diffusion for PMOS using a capped poly layer
    4.
    发明申请
    Method to strain NMOS devices while mitigating dopant diffusion for PMOS using a capped poly layer 有权
    使用封端的多晶硅层减少PMOS器件的掺杂剂扩散的方法来应变NMOS器件

    公开(公告)号：US20060189048A1

    公开(公告)日：2006-08-24

    申请号：US11060841

    申请日：2005-02-18

    申请人： Manoj Mehrotra ,  Lahir Adam ,  Song Zhao ,  Mahalingam Nandakumar

    发明人： Manoj Mehrotra ,  Lahir Adam ,  Song Zhao ,  Mahalingam Nandakumar

    IPC分类号： H01L21/84

    CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7843 ,  Y10S438/902

    摘要： The present invention facilitates semiconductor fabrication by providing methods of fabrication that apply tensile strain to channel regions of devices while mitigating unwanted dopant diffusion, which degrades device performance. Source/drain regions are formed in active regions of a PMOS region (102). A first thermal process is performed that activates the formed source/drain regions and drives in implanted dopants (104). Subsequently, source/drain regions are formed in active regions of an NMOS region (106). Then, a capped poly layer is formed over the device (108). A second thermal process is performed (110) that causes the capped poly layer to induce strain into the channel regions of devices. Because of the first thermal process, unwanted dopant diffusion, particularly unwanted p-type dopant diffusion, during the second thermal process is mitigated.

    摘要翻译： 本发明通过提供制造方法来促进半导体制造，所述方法对设备的沟道区域施加拉伸应变，同时减轻不期望的掺杂剂扩散，这降低了器件性能。 源极/漏极区形成在PMOS区（102）的有源区中。 执行第一热处理，其激活所形成的源极/漏极区域和在注入的掺杂剂（104）中的驱动。 随后，在NMOS区域（106）的有源区域中形成源极/漏极区域。 然后，在器件（108）上形成封端的多晶硅层。 执行第二热处理（110），其使得封端的多晶硅层引入器件的沟道区域的应变。 由于第一热处理，减少了在第二热处理期间不期望的掺杂剂扩散，特别是不期望的p型掺杂剂扩散。