公开(公告)号：US06933591B1

公开(公告)日：2005-08-23

申请号：US10687199

申请日：2003-10-16

申请人： Lakhbeer S. Sidhu ,  Irfan Rahim

发明人： Lakhbeer S. Sidhu ,  Irfan Rahim

IPC分类号： H01L23/525 ,  H01L23/58

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： Programmable fuses for integrated circuits are provided. The fuses may be based on polysilicon or crystalline silicon fuse links coated with silicide or other conductive thin films. Fuses may be formed on silicon-on-insulator (SOI) substrates. A fuse may be blown by applying a programming current to the fuse link. The silicon or polysilicon in the fuses may be provided with a p-n junction. When a fuse is programmed, the silicide or other conductive film forms an open circuit. This forces current though the underlying p-n junction. Unlike conventional silicided polysilicon fuses, fuses with p-n junctions change their qualitative behavior when programmed. Unprogrammed fuses behave like resistors, while programmed fuses behave like diodes. The presence of the p-n junction allows sensing circuitry to determine in a highly accurate qualitative fashion whether a given fuse has been programmed.

摘要翻译： 提供集成电路的可编程保险丝。 保险丝可以基于涂覆有硅化物或其它导电薄膜的多晶硅或晶体硅熔丝链。 可以在绝缘体上硅（SOI）衬底上形成保险丝。 通过向熔丝链路施加编程电流可能会熔断保险丝。 保险丝中的硅或多晶硅可以设置有p-n结。 当熔丝被编程时，硅化物或其它导电膜形成开路。 这通过下面的p-n结强迫电流。 与传统的硅化多晶硅保险丝不同，p-n结的保险丝在编程时会改变其定性行为。 未编程的保险丝与电阻器类似，而编程的保险丝就像二极管。 p-n结的存在允许感测电路以高度精确的定性方式确定给定的保险丝是否已被编程。

公开(公告)号：US07465971B2

公开(公告)日：2008-12-16

申请号：US11951122

申请日：2007-12-05

申请人： Lakhbeer S. Sidhu ,  Irfan Rahim ,  Jeffrey Watt ,  John Turner

发明人： Lakhbeer S. Sidhu ,  Irfan Rahim ,  Jeffrey Watt ,  John Turner

IPC分类号： H01L29/94

CPC分类号： G11C11/412 ,  H01L27/0207 ,  H01L27/11807

摘要： A configuration memory cell (“CRAM”) for a field programmable gate array (“FPGA”) integrated circuit (“IC”) device is given increased resistance to single event upset (“SEU”). A portion of the gate structure of the input node of the CRAM is increased in size relative to the nominal size of the remainder of the gate structure. Part of the enlarged gate structure is located capacitively adjacent to an N-well region of the IC, and another part is located capacitively adjacent to a P-well region of the IC. This arrangement gives the input node increased capacitance to resist SEU, regardless of the logical level of the input node. The invention is also applicable to any node of any type of memory cell for which increased resistance to SEU is desired.

公开(公告)号：US07153712B1

公开(公告)日：2006-12-26

申请号：US11123505

申请日：2005-05-05

申请人： Lakhbeer S. Sidhu ,  Irfan Rahim

发明人： Lakhbeer S. Sidhu ,  Irfan Rahim

IPC分类号： H01L21/66

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： Programmable fuses for integrated circuits are provided. The fuses may be based on polysilicon or crystalline silicon fuse links coated with silicide or other conductive thin films. Fuses may be formed on silicon-on-insulator (SOI) substrates. A fuse may be blown by applying a programming current to the fuse link. The silicon or polysilicon in the fuses may be provided with a p-n junction. When a fuse is programmed, the silicide or other conductive film forms an open circuit. This forces current though the underlying p-n junction. Unlike conventional silicided polysilicon fuses, fuses with p-n junctions change their qualitative behavior when programmed. Unprogrammed fuses behave like resistors, while programmed fuses behave like diodes. The presence of the p-n junction allows sensing circuitry to determine in a highly accurate qualitative fashion whether a given fuse has been programmed.

摘要翻译： 提供集成电路的可编程保险丝。 保险丝可以基于涂覆有硅化物或其它导电薄膜的多晶硅或晶体硅熔丝链。 可以在绝缘体上硅（SOI）衬底上形成保险丝。 通过向熔丝链路施加编程电流可能会熔断保险丝。 保险丝中的硅或多晶硅可以设置有p-n结。 当熔丝被编程时，硅化物或其它导电膜形成开路。 这通过下面的p-n结强迫电流。 与传统的硅化多晶硅保险丝不同，p-n结的保险丝在编程时会改变其定性行为。 未编程的保险丝与电阻器类似，而编程的保险丝就像二极管。 p-n结的存在允许感测电路以高度精确的定性方式确定给定的保险丝是否已被编程。

公开(公告)号：US07135951B1

公开(公告)日：2006-11-14

申请号：US10620859

申请日：2003-07-15

申请人： Lakhbeer S. Sidhu ,  Irfan Rahim

发明人： Lakhbeer S. Sidhu ,  Irfan Rahim

IPC分类号： H01F5/00 ,  H01F7/06

CPC分类号： H01L23/5227 ,  H01F17/0013 ,  H01F27/34 ,  H01F27/362 ,  H01F27/40 ,  H01F41/041 ,  H01F2017/002 ,  H01F2017/0053 ,  H01L21/761 ,  H01L27/08 ,  H01L2924/0002 ,  Y10T29/4902 ,  Y10T29/49071 ,  H01L2924/00

摘要： Integrated circuit inductors may be formed using a spiral layout on the surface of an interconnect dielectric stack. Conductive lines from two or more metal layers in the interconnect stack may be electrically connected using one or more via trenches. The via trench interconnection arrangement reduces the resistance of the inductor and increases the inductor's Q-factor. The Q-factor of the inductor may also be increased by placing a region of n-type and p-type wells or a metal plate region beneath the inductor to reduce power losses during operation. Shallow trench isolation may be used to reduce eddy currents and increase Q. The effects of copper dishing and trench blow-out may be used during inductor fabrication. A dual damascene fabrication process may be used.

摘要翻译： 集成电路电感器可以使用在互连电介质叠层的表面上的螺旋布局形成。 可以使用一个或多个通孔沟槽来电连接互连叠层中的两个或多个金属层的导电线。 通孔沟槽互连布置降低了电感器的电阻并增加了电感器的Q因子。 电感器的Q因子也可以通过在电感器下方放置n型和p型阱区域或金属板区域来减小操作期间的功率损耗。 可以使用浅沟槽隔离来减少涡流并增加Q.在电感器制造期间可以使用铜凹陷和沟槽吹出的影响。 可以使用双镶嵌制造工艺。

公开(公告)号：US08149011B1

公开(公告)日：2012-04-03

申请号：US12953117

申请日：2010-11-23

申请人： Lakhbeer S. Sidhu ,  Choy Hing Li

发明人： Lakhbeer S. Sidhu ,  Choy Hing Li

IPC分类号： G01R31/02

CPC分类号： G01R31/2621

摘要： A method comprising applying a first voltage to a first transistor to create a defect in the first transistor, wherein (i) the first voltage is greater than a maximum operational voltage of the first transistor and (ii) the maximum operational voltage does not cause a defect in the first transistor when applied to the first transistor. The method further includes determining whether the first transistor has been programmed, including (i) measuring a first current through the first transistor, (ii) measuring a second current through a second transistor, and (iii) comparing the measured first current to the measured second current, wherein a difference between the measured first current and the measured second current indicates that the first transistor has been programmed.

摘要翻译： 一种方法，包括向第一晶体管施加第一电压以在第一晶体管中产生缺陷，其中（i）第一电压大于第一晶体管的最大工作电压，以及（ii）最大工作电压不会导致 当施加到第一晶体管时，第一晶体管的缺陷。 该方法还包括确定第一晶体管是否已经被编程，包括（i）测量通过第一晶体管的第一电流，（ii）测量通过第二晶体管的第二电流，以及（iii）将测量的第一电流与测量的 第二电流，其中测量的第一电流和测量的第二电流之间的差指示第一晶体管已被编程。

公开(公告)号：US07839160B1

公开(公告)日：2010-11-23

申请号：US12053428

申请日：2008-03-21

申请人： Lakhbeer S. Sidhu ,  Choy Hing Li

发明人： Lakhbeer S. Sidhu ,  Choy Hing Li

IPC分类号： G01R31/26

CPC分类号： G01R31/2621

摘要： Methods for stressing transistors in order to program the transistors and for determining whether such transistors have indeed been programmed are described herein. The novel methods may include initially stressing a transistor by applying to the transistor a voltage greater than operational voltages of the transistor to create defects in the transistor. A current flowing through the transistor may then be measured to determine whether the transistor has been programmed, the measured current indicative of the presence of the defects.

摘要翻译： 这里描述了为了对晶体管进行编程并且用于确定这样的晶体管是否确实被编程的压力晶体管的方法。 新颖的方法可以包括最初通过向晶体管施加大于晶体管的工作电压的电压来施加晶体管，从而在晶体管中产生缺陷。 然后可以测量流过晶体管的电流，以确定晶体管是否已被编程，所测量的电流指示缺陷的存在。