Signal processing device and method
    1.
    发明授权
    Signal processing device and method 有权
    信号处理装置及方法

    公开(公告)号:US08509725B2

    公开(公告)日:2013-08-13

    申请号:US13001758

    申请日:2009-06-15

    IPC分类号: H04B1/26

    CPC分类号: H04B1/28 H04B1/406

    摘要: A processing device (40) for processing an analog complex input signal generated by downconversion of an aggregated-spectrum radio-frequency signal in a radio-receiver (10), wherein the complex input signal comprises a plurality of sub bands (S1-S4) scattered across a total frequency band (4) of the complex input signal. The processing device (40) comprises a plurality of processing paths (P1-PN). wherein each processing path (P1-PN) is adapted to process an associated sub band (S1-S4). Each processing path comprises a complex mixer (CM1-CMN) adapted to frequency translate the complex input signal, and an analog channel-selection filter (CSF1-CSFN) arranged to filter an output signal of the complex mixer (CM1-CMN) and pass the frequency translated associated sub band (S1-S4). A control unit (60) is adapted to receive control data indicating frequency locations of the sub bands (S1-S4) and, for each processing path (P1-PN). control the local oscillator signal of the complex mixer (CM1-CMN) of the processing path (P1-PN) based on the frequency location of the associated sub band (S1-S4) and the passband of the channel-selection filter (CSF1-CSFN) of the processing path (P1-PN), such that the frequency-translated associated sub band (S1-S4) appears within a passband of the channel-selection filter (CSF1-CSFN) of the processing path (P1-PN). The distortion monitored in the unused paths may be used to improve the performance of the used paths.

    摘要翻译: 一种处理装置(40),用于处理通过在无线电接收机(10)中对聚合频谱射频信号进行下变频而产生的模拟复合输入信号,其中所述复合输入信号包括多个子带(S1-S4) 分散在复合输入信号的总频带(4)上。 处理装置(40)包括多个处理路径(P1-PN),其中每个处理路径(P1-PN)适于处理相关子带(S1-S4)。 每个处理路径包括适于对复数输入信号进行频率转换的复合混频器(CM1-CMN),和布置成对复合混频器(CM1-CMN)的输出信号进行滤波并通过的模拟通道选择滤波器(CSF1-CSFN) 频率相关子带(S1-S4)。 控制单元(60)适于接收指示子频带的频率位置的控制数据(S1-S4),并且对于每个处理路径(P1-PN),控制复合混频器(CM1-CMN)的本地振荡器信号, 基于相关子带(S1-S4)的频率位置和处理路径(P1-PN)的信道选择滤波器(CSF1-CSFN)的通带的处理路径(P1-PN),使得 经频率转换的相关子带(S1-S4)出现在处理路径(P1-PN)的信道选择滤波器(CSF1-CSFN)的通带内。 在未使用的路径中监视的失真可用于改善所使用路径的性能。

    Signal Processing Device and Method
    2.
    发明申请
    Signal Processing Device and Method 有权
    信号处理装置及方法

    公开(公告)号:US20110136455A1

    公开(公告)日:2011-06-09

    申请号:US13001758

    申请日:2009-06-15

    IPC分类号: H04B1/26

    CPC分类号: H04B1/28 H04B1/406

    摘要: A processing device (40) for processing an analog complex input signal generated by downconversion of an aggregated-spectrum radio-frequency signal in a radio-receiver (10), wherein the complex input signal comprises a plurality of sub bands (S1-S4) scattered across a total frequency band (4) of the complex input signal. The processing device (40) comprises a plurality of processing paths (P1-PN). wherein each processing path (P1-PN) is adapted to process an associated sub band (S1-S4). Each processing path comprises a complex mixer (CM1-CMN) adapted to frequency translate the complex input signal, and an analog channel-selection filter (CSF1-CSFN) arranged to filter an output signal of the complex mixer (CM1-CMN) and pass the frequency translated associated sub band (S1-S4). A control unit (60) is adapted to receive control data indicating frequency locations of the sub bands (S1-S4) and, for each processing path (P1-PN). control the local oscillator signal of the complex mixer (CM1-CMN) of the processing path (P1-PN) based on the frequency location of the associated sub band (S1-S4) and the passband of the channel-selection filter (CSF1-CSFN) of the processing path (P1-PN), such that the frequency-translated associated sub band (S1-S4) appears within a passband of the channel-selection filter (CSF1-CSFN) of the processing path (P1-PN). The distortion monitored in the unused paths may be used to improve the performance of the used paths.

    摘要翻译: 一种处理装置(40),用于处理通过在无线电接收机(10)中对聚合频谱射频信号进行下变频而产生的模拟复合输入信号,其中所述复合输入信号包括多个子带(S1-S4) 分散在复合输入信号的总频带(4)上。 处理装置(40)包括多个处理路径(P1-PN),其中每个处理路径(P1-PN)适于处理相关子带(S1-S4)。 每个处理路径包括适于对复数输入信号进行频率转换的复合混频器(CM1-CMN),和布置成对复合混频器(CM1-CMN)的输出信号进行滤波并通过的模拟通道选择滤波器(CSF1-CSFN) 频率相关子带(S1-S4)。 控制单元(60)适于接收指示子频带的频率位置的控制数据(S1-S4),并且对于每个处理路径(P1-PN),控制复合混频器(CM1-CMN)的本地振荡器信号, 基于相关子带(S1-S4)的频率位置和处理路径(P1-PN)的信道选择滤波器(CSF1-CSFN)的通带的处理路径(P1-PN),使得 经频率转换的相关子带(S1-S4)出现在处理路径(P1-PN)的信道选择滤波器(CSF1-CSFN)的通带内。 在未使用的路径中监视的失真可用于改善所使用路径的性能。

    Digitally controllable on-chip resistors and methods
    3.
    发明授权
    Digitally controllable on-chip resistors and methods 有权
    数字可控的片上电阻和方法

    公开(公告)号:US07602327B2

    公开(公告)日:2009-10-13

    申请号:US11800954

    申请日:2007-05-08

    IPC分类号: H03M1/78

    CPC分类号: H01C10/50

    摘要: A digitally controllable resistor includes a substrate and at least one digitally controllable resistance stage formed on the substrate. Each of the stage(s) can include a first resistor connected in series with a switch and a second resistor connected in parallel with the first resistor and the switch. Each stage can also include a control line connected to the switch for opening and closing the switch in response to a control bit associated therewith. Multiple resistance stages can be connected in series and the digitally controllable variable resistor can be integrated onto a substrate.

    摘要翻译: 数字可控电阻器包括衬底和形成在衬底上的至少一个数字可控电阻级。 每个级可以包括与开关串联连接的第一电阻器和与第一电阻器和开关并联连接的第二电阻器。 每个级还可以包括连接到开关的控制线,以响应于与其相关联的控制位来打开和闭合开关。 多个电阻级可以串联连接,并且数字可控可变电阻可以集成到基板上。

    Digitally controllable on-chip resistors and methods
    4.
    发明申请
    Digitally controllable on-chip resistors and methods 有权
    数字可控的片上电阻和方法

    公开(公告)号:US20080278277A1

    公开(公告)日:2008-11-13

    申请号:US11800954

    申请日:2007-05-08

    IPC分类号: H01C13/02

    CPC分类号: H01C10/50

    摘要: A digitally controllable resistor includes a substrate and at least one digitally controllable resistance stage formed on the substrate. Each of the stage(s) can include a first resistor connected in series with a switch and a second resistor connected in parallel with the first resistor and the switch. Each stage can also include a control line connected to the switch for opening and closing the switch in response to a control bit associated therewith. Multiple resistance stages can be connected in series and the digitally controllable variable resistor can be integrated onto a substrate.

    摘要翻译: 数字可控电阻器包括衬底和形成在衬底上的至少一个数字可控电阻级。 每个级可以包括与开关串联连接的第一电阻器和与第一电阻器和开关并联连接的第二电阻器。 每个级还可以包括连接到开关的控制线,以响应于与其相关联的控制位来打开和闭合开关。 多个电阻级可以串联连接,并且数字可控可变电阻可以集成到基板上。

    Transceiver Front-End
    5.
    发明申请
    Transceiver Front-End 有权
    收发器前端

    公开(公告)号:US20140011462A1

    公开(公告)日:2014-01-09

    申请号:US13586480

    申请日:2012-08-15

    IPC分类号: H04B1/44

    CPC分类号: H04B1/525 H04B2203/5491

    摘要: A transceiver front-end for a communication device comprises a transmit frequency blocking arrangement and a receive frequency blocking arrangement. The transmit frequency blocking arrangement has a blocking frequency interval associated with the transmit frequency and a non-blocking frequency interval associated with the receive frequency, and is configured to block passage of transmit frequency signals between the signal transmission and reception arrangement and the receiver. The receive frequency blocking arrangement has a blocking frequency interval associated with the receive frequency and a non-blocking frequency interval associated with the transmit frequency, and is configured to block passage of receive frequency signals between the signal transmission and reception arrangement and the transmitter. One of the frequency blocking arrangements comprises a network of passive components including at least one transformer and a filter arrangement with a higher impedance at the blocking frequency interval than at the non-blocking frequency interval.

    摘要翻译: 用于通信设备的收发机前端包括发射频率阻塞装置和接收频率阻塞装置。 发射频率阻塞装置具有与发射频率相关联的阻塞频率间隔和与接收频率相关联的非阻塞频率间隔,并且被配置为阻止发射频率信号在信号发射和接收装置与接收机之间的通过。 接收频率阻挡装置具有与接收频率相关联的阻塞频率间隔和与发射频率相关联的非阻塞频率间隔,并且被配置为阻止信号发送和接收装置与发射机之间的接收频率信号的通过。 频率阻挡装置之一包括无源部件网络,其包括至少一个变压器和在阻塞频率间隔处具有比在非阻塞频率间隔处具有更高阻抗的滤波器装置。

    MIXER ARRANGEMENT
    6.
    发明申请
    MIXER ARRANGEMENT 有权
    混合装置

    公开(公告)号:US20130009688A1

    公开(公告)日:2013-01-10

    申请号:US13514070

    申请日:2010-12-07

    IPC分类号: G06G7/16

    摘要: A mixer arrangement for generating an analog output signal mixing an analog input signal with a discrete-time mixing signal. The mixer arrangement comprises a plurality of unit elements. Each unit element is adapted to be in an enabled mode in a first state of an enable signal supplied to the unit element, and in a disabled mode in a second state of the enable signal. Each unit element is adapted to generate the output signal of the unit element based on the analog input signal of the mixer arrangement in the enabled mode but not in the disabled mode. The unit elements are connected for generating a common output signal as the sum of the output signals from the unit elements. The arrangement is adapted to generate the analog output signal of the mixer arrangement based on the common output signal. A corresponding method is also disclosed.

    摘要翻译: 一种用于产生将模拟输入信号与离散时间混合信号混合的模拟输出信号的混频器装置。 混合器装置包括多个单元元件。 每个单元元件适于在提供给单元元件的使能信号的第一状态中处于使能模式,并且在使能信号的第二状态中处于禁用模式。 每个单元元件适于基于混合器装置的模拟输入信号在使能模式中而不是在禁用模式下产生单元元件的输出信号。 连接单位元件以产生公共输出信号作为来自单元元件的输出信号的总和。 该装置适于基于公共输出信号产生混频器装置的模拟输出信号。 还公开了相应的方法。

    Transceiver front-end
    7.
    发明授权
    Transceiver front-end 有权
    收发器前端

    公开(公告)号:US08909161B2

    公开(公告)日:2014-12-09

    申请号:US13586480

    申请日:2012-08-15

    IPC分类号: H04B1/38

    CPC分类号: H04B1/525 H04B2203/5491

    摘要: A transceiver front-end for a communication device comprises a transmit frequency blocking arrangement and a receive frequency blocking arrangement. The transmit frequency blocking arrangement has a blocking frequency interval associated with the transmit frequency and a non-blocking frequency interval associated with the receive frequency, and is configured to block passage of transmit frequency signals between the signal transmission and reception arrangement and the receiver. The receive frequency blocking arrangement has a blocking frequency interval associated with the receive frequency and a non-blocking frequency interval associated with the transmit frequency, and is configured to block passage of receive frequency signals between the signal transmission and reception arrangement and the transmitter. One of the frequency blocking arrangements comprises a network of passive components including at least one transformer and a filter arrangement with a higher impedance at the blocking frequency interval than at the non-blocking frequency interval.

    摘要翻译: 用于通信设备的收发机前端包括发射频率阻塞装置和接收频率阻塞装置。 发射频率阻塞装置具有与发射频率相关联的阻塞频率间隔和与接收频率相关联的非阻塞频率间隔,并且被配置为阻止发射频率信号在信号发射和接收装置与接收机之间的通过。 接收频率阻挡装置具有与接收频率相关联的阻塞频率间隔和与发射频率相关联的非阻塞频率间隔,并且被配置为阻止信号发送和接收装置与发射机之间的接收频率信号的通过。 频率阻挡装置之一包括无源部件网络,其包括至少一个变压器和在阻塞频率间隔处具有比在非阻塞频率间隔处具有更高阻抗的滤波器装置。

    Technique for Radio Transceiver Adaptation
    8.
    发明申请
    Technique for Radio Transceiver Adaptation 审中-公开
    无线电收发器适应技术

    公开(公告)号:US20140011464A1

    公开(公告)日:2014-01-09

    申请号:US14000712

    申请日:2012-02-17

    IPC分类号: H04B1/44

    CPC分类号: H04B1/44 H04B1/525

    摘要: A technique for adjusting a transceiver capable of operating in compliance with at least one radio communication standard and comprising at least one RF transmitter and at least one RF receiver is disclosed. The technique comprises determining, when the RF transmitter transmits a signal, the amount of signal power leakage from the RF transmitter into the RF receiver, and adjusting, when RF transmitter is configured to transmit in a specific frequency range, one or more parameters of the RF receiver so as to fulfil a receiver requirement as defined in the radio communication standard. The adjustment is at least partially based on the signal power leakage determined for the specific frequency range.

    摘要翻译: 公开了一种用于调整能够符合至少一个无线电通信标准并且包括至少一个RF发射机和至少一个RF接收机的收发器的技术。 该技术包括确定当RF发射器发射信号时,从RF发射机到RF接收机的信号功率泄漏量,以及当RF发射机被配置为在特定频率范围内发射时,调整一个或多个参数 RF接收机,以满足无线电通信标准中定义的接收机要求。 该调整至少部分地基于针对特定频率范围确定的信号功率泄漏。

    Transceiver Front-End
    9.
    发明申请
    Transceiver Front-End 有权
    收发器前端

    公开(公告)号:US20150222321A1

    公开(公告)日:2015-08-06

    申请号:US14413293

    申请日:2012-07-09

    IPC分类号: H04B1/525 H04L5/14

    CPC分类号: H04B1/525 H04L5/14

    摘要: A transceiver front-end of a communication device is disclosed. The transceiver front-end is connectable to a signal transmission and reception arrangement adapted to transmit a transmit signal having a transmit frequency and to receive a receive signal having a receive frequency, to a transmitter adapted to produce the transmit signal, and to a receiver adapted to process the receive signal. The transceiver front-end comprises at least one of a transmit frequency blocking arrangement and a receive frequency blocking arrangement. The transmit frequency blocking arrangement has a blocking frequency interval associated with the transmit frequency and a non-blocking frequency interval associated with the receive frequency, and is adapted to block passage of transmit frequency signals between the signal transmission and reception arrangement and the receiver. The receive frequency blocking arrangement has a blocking frequency interval associated with the receive frequency and a non-blocking frequency interval associated with the transmit frequency, and is adapted to block passage of receive frequency signals between the signal transmission and reception arrangement and the transmitter. At least one of the transmit frequency blocking arrangement and the receive frequency blocking arrangement comprises a network of passive components comprising at least one transformer and a frequency translated impedance adapted to have a higher impedance value in the blocking frequency interval than in the non-blocking frequency interval.

    摘要翻译: 公开了一种通信设备的收发机前端。 收发器前端可连接到信号发射和接收装置,适于传输具有发射频率的发射信号,并将接收频率的接收信号接收到适于产生发射信号的发射机,以及接收机适配 以处理接收信号。 收发机前端包括发射频率阻挡装置和接收频率阻塞装置中的至少一个。 发射频率阻塞装置具有与发射频率相关联的阻塞频率间隔和与接收频率相关联的非阻塞频率间隔,并且适于阻止信号发射和接收装置与接收机之间的发射频率信号的通过。 接收频率阻塞装置具有与接收频率相关联的阻塞频率间隔和与发射频率相关联的非阻塞频率间隔,并且适于阻止信号发射和接收装置与发射机之间的接收频率信号的通过。 发射频率阻挡装置和接收频率阻挡装置中的至少一个包括无源部件网络,其包括至少一个变压器和频率转换阻抗,该阻抗适于在阻塞频率间隔中具有比在非阻塞频率中更高的阻抗值 间隔。

    Low-noise amplifier with impedance boosting circuit
    10.
    发明授权
    Low-noise amplifier with impedance boosting circuit 有权
    具有阻抗提升电路的低噪声放大器

    公开(公告)号:US09077290B2

    公开(公告)日:2015-07-07

    申请号:US13988595

    申请日:2011-09-23

    摘要: A low-noise amplifier (300) is provided which comprises an input circuit (301) configured to operate with a variable bias current and an impedance boosting circuit (314) electrically connected to the input circuit (301). The impedance boosting circuit (314) comprises at least one switch (316) and at least one tail inductor (318) electrically connected with the at least one switch (316). The low-noise amplifier (300) is configured to activate the impedance boosting circuit (314) if the variable bias current is reduced, and the impedance boosting circuit (314) is configured to increase the input impedance of the low-noise amplifier (300) if the impedance boosting circuit (314) is activated.

    摘要翻译: 提供了一种低噪声放大器(300),其包括被配置为与可变偏置电流一起操作的输入电路(301)和电连接到输入电路(301)的阻抗提升电路(314)。 阻抗提升电路(314)包括与至少一个开关(316)电连接的至少一个开关(316)和至少一个尾电感器(318)。 如果可变偏置电流减小,低噪声放大器(300)被配置为激活阻抗提升电路(314),并且阻抗提升电路(314)被配置为增加低噪声放大器(300)的输入阻抗 ),如果阻抗提升电路(314)被激活。