公开(公告)号：US10250263B2

公开(公告)日：2019-04-02

申请号：US15114394

申请日：2015-05-12

Applicant: Lattice Semiconductor Corporation

Inventor： Kexin Luo ,  Rui Yin ,  Xiaofeng Wang ,  Jie Yuan ,  Qiming Wu ,  Fei Song ,  Min-Kyu Kim

IPC: H03L7/00 ,  H03K3/011 ,  H03B5/04 ,  H03L1/00 ,  H03L7/093 ,  H03K3/03 ,  H03K3/0231 ,  H03L7/099

Abstract: Embodiments relate to a voltage oscillator (VCO) that uses a replica bias circuit to generate a cascode bias voltage. The VCO generate an output periodic signal having a frequency and phase that is less or not susceptible to voltage swings by using a bias voltage generated in a replica bias circuit that replicates a voltage-to-current converter in the VOC. The bias voltage is generated and regulated according to a power supply voltage that supplies power to the VCO to account for voltage variations in the power supply voltage.

公开(公告)号：US20170149437A1

公开(公告)日：2017-05-25

申请号：US15114394

申请日：2015-05-12

Applicant: Lattice Semiconductor Corporation

Inventor： Kexin Luo ,  Rui Yin ,  Xiaofeng Wang ,  Jie Yuan ,  Qiming Wu ,  Fei Song ,  Min-Kyu Kim

IPC: H03L7/00

CPC classification number: H03L7/00 ,  H03B5/04 ,  H03K3/011 ,  H03K3/0231 ,  H03K3/03 ,  H03L1/00 ,  H03L7/093 ,  H03L7/099

Abstract: Embodiments relate to a voltage oscillator (VCO) that uses a replica bias circuit to generate a cascode bias voltage. The VCO generate an output periodic signal having a frequency and phase that is less or not susceptible to voltage swings by using a bias voltage generated in a replica bias circuit that replicates a voltage-to-current converter in the VOC. The bias voltage is generated and regulated according to a power supply voltage that supplies power to the VCO to account for voltage variations in the power supply voltage.

公开(公告)号：US09559707B2

公开(公告)日：2017-01-31

申请号：US14423422

申请日：2014-10-23

Applicant: Lattice Semiconductor Corporation

Inventor： Kexin Luo ,  Yan Rui ,  Shaoyong Lu ,  Rui Yin ,  Yu Shen

IPC: H03L7/06 ,  H03L7/089 ,  H03L7/093 ,  H03L7/099 ,  H03L7/18

CPC classification number: H03L7/0891 ,  H03L7/089 ,  H03L7/093 ,  H03L7/099 ,  H03L7/18 ,  H03L2207/14

Abstract: Embodiments relate to type-I PLLs that do not lock at a sub-harmonic frequency of a reference clock signal by controlling timing of charging or discharging of one or more capacitors in the PLLs. A phase frequency detector (PFD) of a type-I PLL can prevent sub-harmonic locking by generating a clear output signal to cause a sampling capacitor of PLL's loop filter to discharge only during a time period when the sampling capacitor is not being charged. For example, the PFD can include a gating element to control the time during which the clear output signal is generated. By ensuring that the sampling capacitor is not discharged during a time period while it is being charged, the PLL's voltage-controlled oscillator is controlled to oscillate at an intended frequency rather than at a sub-harmonic of the intended frequency.

Abstract translation: 实施例涉及通过控制PLL中的一个或多个电容器的充电或放电的定时而不锁定在参考时钟信号的次谐波频率的I型PLL。 I型PLL的相位频率检测器（PFD）可以通过产生清零的输出信号来防止副谐波锁定，使PLL环路滤波器的采样电容仅在采样电容器未充电的时间段内放电。 例如，PFD可以包括门控元件来控制产生清除输出信号的时间。 通过确保采样电容器在充电期间的时间段内不会放电，PLL的压控振荡器被控制为以预期频率而不是预期频率的次谐波振荡。

公开(公告)号：US20160254818A1

公开(公告)日：2016-09-01

申请号：US14423422

申请日：2014-10-23

Applicant: LATTICE SEMICONDUCTOR CORPORATION

Inventor： Kexin Luo ,  Yan Rui ,  Shaoyong Lu ,  Rui Yin ,  Yu Shen

IPC: H03L7/089 ,  H03L7/18 ,  H03L7/099

CPC classification number: H03L7/0891 ,  H03L7/089 ,  H03L7/093 ,  H03L7/099 ,  H03L7/18 ,  H03L2207/14

Abstract: Embodiments relate to type-I PLLs that do not lock at a sub-harmonic frequency of a reference clock signal by controlling timing of charging or discharging of one or more capacitors in the PLLs. A phase frequency detector (PFD) of a type-I PLL can prevent sub-harmonic locking by generating a clear output signal to cause a sampling capacitor of PLL's loop filter to discharge only during a time period when the sampling capacitor is not being charged. For example, the PFD can include a gating element to control the time during which the clear output signal is generated. By ensuring that the sampling capacitor is not discharged during a time period while it is being charged, the PLL's voltage-controlled oscillator is controlled to oscillate at an intended frequency rather than at a sub-harmonic of the intended frequency.

Abstract translation: 实施例涉及通过控制PLL中的一个或多个电容器的充电或放电的定时而不锁定在参考时钟信号的次谐波频率的I型PLL。 I型PLL的相位频率检测器（PFD）可以通过产生清零的输出信号来防止副谐波锁定，使PLL环路滤波器的采样电容仅在采样电容器未充电的时间段内放电。 例如，PFD可以包括门控元件来控制产生清除输出信号的时间。 通过确保采样电容器在充电期间的时间段内不会放电，PLL的压控振荡器被控制为以预期频率而不是预期频率的次谐波振荡。