公开(公告)号：US09852103B2

公开(公告)日：2017-12-26

申请号：US14681992

申请日：2015-04-08

Applicant: Lattice Semiconductor Corporation

Inventor： Ju Hwan Yi ,  Young Il Kim ,  Gijung Ahn ,  Min-Kyu Kim ,  Daeyun Shim ,  Gyudong Kim ,  Hoon Choi

IPC: G06F13/14 ,  G06F13/42 ,  G06F13/40 ,  G09G5/00 ,  G06F3/14

CPC classification number: G06F13/4278 ,  G06F3/14 ,  G06F13/4068 ,  G09G5/006 ,  G09G2370/04 ,  G09G2370/047 ,  G09G2370/10

Abstract: Embodiments relate to half-duplex bidirectional transmission of data compliant with a first standard (e.g., Universal Serial Bus (USB) standard) over a physical channel of a multimedia link for transmitting audio/video (“A/V”) data compliant with a second standard (e.g., Mobile High-Definition Link (MHL) standard) between a source device and a sink device using time division multiplexing (TDM). The source device sends units of data including A/V data and forward data compliant with the first standard at first times whereas the sink device sends units of data including backward data compliant with the first standard at second times between transmissions from the source device. The first times do not overlap with the second times. Synchronization signals may be added to the first and second units of data to align character symbols embedded in the first and second units of data.

公开(公告)号：US10116428B2

公开(公告)日：2018-10-30

申请号：US15312149

申请日：2014-05-20

Applicant: Lattice Semiconductor Corporation

Inventor： Qiming Wu ,  Kai Lei ,  Fei Song ,  Kai Zhou ,  Gijung Ahn ,  Zhi Wu ,  Min-Kyu Kim

IPC: H04L5/14 ,  H04B3/23 ,  H04B3/30

Abstract: Systems, devices and methods for analog echo cancellation for high speed full duplex data transmissions, which include a first set of differential nodes to receive reception data and transmission data, a second set of differential nodes to receive the transmission data, and a subtraction circuit to receive data from the first set of differential nodes and data from the second set of differential nodes. The subtraction circuit includes a plurality of capacitors to receive data from each of the first and second sets differential nodes, and a termination circuit for providing DC termination voltage to subtract the data of the second set of differential nodes from the data of the first set of differential nodes to eliminate echo from the reception data received at the first set differential nodes.

公开(公告)号：US20170085359A1

公开(公告)日：2017-03-23

申请号：US15312149

申请日：2014-05-20

Applicant: LATTICE SEMICONDUCTOR CORPORATION

Inventor： Qiming Wu ,  Kai Lei ,  Fei Song ,  Kai Zhou ,  Gijung Ahn ,  Zhi Wu ,  Min-Kyu Kim

IPC: H04L5/14

CPC classification number: H04L5/1461 ,  H04B3/23 ,  H04B3/30

Abstract: Systems, devices and methods for analog echo cancellation for high speed full duplex data transmissions, which include a first set of differential nodes to receive reception data and transmission data, a second set of differential nodes to receive the transmission data, and a subtraction circuit to receive data from the first set of differential nodes and data from the second set of differential nodes. The subtraction circuit includes a plurality of capacitors to receive data from each of the first and second sets differential nodes, and a termination circuit for providing DC termination voltage to subtract the data of the second set of differential nodes from the data of the first set of differential nodes to eliminate echo from the reception data received at the first set differential nodes.

公开(公告)号：US20170149437A1

公开(公告)日：2017-05-25

申请号：US15114394

申请日：2015-05-12

Applicant: Lattice Semiconductor Corporation

Inventor： Kexin Luo ,  Rui Yin ,  Xiaofeng Wang ,  Jie Yuan ,  Qiming Wu ,  Fei Song ,  Min-Kyu Kim

IPC: H03L7/00

CPC classification number: H03L7/00 ,  H03B5/04 ,  H03K3/011 ,  H03K3/0231 ,  H03K3/03 ,  H03L1/00 ,  H03L7/093 ,  H03L7/099

Abstract: Embodiments relate to a voltage oscillator (VCO) that uses a replica bias circuit to generate a cascode bias voltage. The VCO generate an output periodic signal having a frequency and phase that is less or not susceptible to voltage swings by using a bias voltage generated in a replica bias circuit that replicates a voltage-to-current converter in the VOC. The bias voltage is generated and regulated according to a power supply voltage that supplies power to the VCO to account for voltage variations in the power supply voltage.

公开(公告)号：US09887733B2

公开(公告)日：2018-02-06

申请号：US15582371

申请日：2017-04-28

Applicant: Lattice Semiconductor Corporation

Inventor： Kai Zhou ,  Shinje Tahk ,  Kai Lei ,  Qiming Wu ,  Gijung Ahn ,  Min-Kyu Kim ,  Fei Song ,  Kexin Luo

IPC: H04L5/14 ,  H04B3/23 ,  H04L5/00

CPC classification number: H04B3/232 ,  H04B1/525 ,  H04L5/0091 ,  H04L5/14 ,  H04L5/1461 ,  H04M9/082

Abstract: A method that calibrates a device for echo cancellation and a device with calibration for echo cancellation are provided. Devices may be calibrated such that the echo residual error is less than a threshold determined by the calibration accuracy. Non-ideal factors such as mismatch may be eliminated during calibration.

公开(公告)号：US10250263B2

公开(公告)日：2019-04-02

申请号：US15114394

申请日：2015-05-12

Applicant: Lattice Semiconductor Corporation

Inventor： Kexin Luo ,  Rui Yin ,  Xiaofeng Wang ,  Jie Yuan ,  Qiming Wu ,  Fei Song ,  Min-Kyu Kim

IPC: H03L7/00 ,  H03K3/011 ,  H03B5/04 ,  H03L1/00 ,  H03L7/093 ,  H03K3/03 ,  H03K3/0231 ,  H03L7/099

Abstract: Embodiments relate to a voltage oscillator (VCO) that uses a replica bias circuit to generate a cascode bias voltage. The VCO generate an output periodic signal having a frequency and phase that is less or not susceptible to voltage swings by using a bias voltage generated in a replica bias circuit that replicates a voltage-to-current converter in the VOC. The bias voltage is generated and regulated according to a power supply voltage that supplies power to the VCO to account for voltage variations in the power supply voltage.

公开(公告)号：US09379752B2

公开(公告)日：2016-06-28

申请号：US14118832

申请日：2012-12-28

Applicant: Lattice Semiconductor Corporation

Inventor： Xiaozhi Lin ,  Fei Song ,  Gyudong Kim ,  Chwei-po Chew ,  Min-Kyu Kim

IPC: H04L25/00 ,  H04B1/12 ,  H03F3/45 ,  H04L27/26

CPC classification number: H04B1/123 ,  H03F3/45475 ,  H03F3/45717 ,  H03F2203/45418 ,  H04L27/2691

Abstract: Embodiments of the invention are generally directed to compensation for common mode signal swing. An embodiment of an apparatus includes a connector for the transfer of the data, the connector including connections for a first set of one or more conductors; a receiver for the reception of data via the connector, the received data including a first signal and a second signal transmitted via the set of one or more conductors, the second signal being a common mode signal modulating the first signal, the receiver including an amplifier to amplify the received data with a positive gain; and a common mode compensation circuit to compensate for a voltage swing of the common mode signal in the amplified received data. The common mode compensation circuit is to sense the common mode signal, amplify the sensed common mode signal with a negative gain, and feed back the amplified common mode to output nodes of the receiver.

Abstract translation: 本发明的实施例通常涉及对共模信号摆幅的补偿。 装置的实施例包括用于传送数据的连接器，连接器包括用于第一组一个或多个导体的连接; 用于经由连接器接收数据的接收器，所接收的数据包括通过一组或多个导体发送的第一信号和第二信号，第二信号是调制第一信号的共模信号，接收器包括放大器 以正增益放大接收到的数据; 以及用于补偿放大的接收数据中的共模信号的电压摆幅的共模补偿电路。 共模补偿电路用于检测共模信号，以负增益放大感测的共模信号，并将放大的共模反馈到接收器的输出节点。