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    Linear regulator with improved power supply ripple rejection
    1.
    发明授权
    Linear regulator with improved power supply ripple rejection 有权
    线性稳压器，具有改善的电源纹波抑制

    公开(公告)号：US09477244B2

    公开(公告)日：2016-10-25

    申请号：US14381186

    申请日：2014-01-10

    Applicant: Lattice Semiconductor Corporation

    Inventor： Kexin Luo ,  Fangqing Chu ,  Yu Shen ,  Zhi Wu ,  Inyeol Lee

    IPC: G05F1/46 ,  G05F1/56

    CPC classification number: G05F1/468 ,  G05F1/56

    Abstract: Embodiments of the invention are generally directed to a linear regulator with improved power supply ripple rejection. An embodiment of an apparatus includes an linear regulator to receive a system power supply and to generate a regulated power supply; a first voltage reference generator to generate a first voltage reference for the linear regulator; a second voltage reference generator to generate a second voltage reference for the linear regulator; and a voltage reference and power switcher. In some embodiments, the voltage reference and power switcher is to switch a voltage reference for the linear regulator from the first voltage reference to the second voltage reference and is to switch a part of a power supply for the linear regulator from the system power supply to the regulated power supply.

    Abstract translation: 本发明的实施例通常涉及具有改进的电源纹波抑制的线性调节器。 装置的实施例包括线性调节器，用于接收系统电源并产生稳压电源; 第一参考电压发生器，用于产生线性调节器的第一电压基准; 第二参考发生器，用于为所述线性调节器产生第二参考电压; 以及电压基准和电源切换器。 在一些实施例中，电压参考和功率切换器将线性调节器的电压参​​考值从第一参考电压切换到第二参考电压，并将用于线性稳压器的电源的一部分从系统电源切换到 稳压电源。

    Phase locked loop with sub-harmonic locking prevention functionality
    3.
    发明授权
    Phase locked loop with sub-harmonic locking prevention functionality 有权
    具有次谐波锁定防止功能的锁相环

    公开(公告)号：US09559707B2

    公开(公告)日：2017-01-31

    申请号：US14423422

    申请日：2014-10-23

    Applicant: Lattice Semiconductor Corporation

    Inventor： Kexin Luo ,  Yan Rui ,  Shaoyong Lu ,  Rui Yin ,  Yu Shen

    IPC: H03L7/06 ,  H03L7/089 ,  H03L7/093 ,  H03L7/099 ,  H03L7/18

    CPC classification number: H03L7/0891 ,  H03L7/089 ,  H03L7/093 ,  H03L7/099 ,  H03L7/18 ,  H03L2207/14

    Abstract: Embodiments relate to type-I PLLs that do not lock at a sub-harmonic frequency of a reference clock signal by controlling timing of charging or discharging of one or more capacitors in the PLLs. A phase frequency detector (PFD) of a type-I PLL can prevent sub-harmonic locking by generating a clear output signal to cause a sampling capacitor of PLL's loop filter to discharge only during a time period when the sampling capacitor is not being charged. For example, the PFD can include a gating element to control the time during which the clear output signal is generated. By ensuring that the sampling capacitor is not discharged during a time period while it is being charged, the PLL's voltage-controlled oscillator is controlled to oscillate at an intended frequency rather than at a sub-harmonic of the intended frequency.

    Abstract translation: 实施例涉及通过控制PLL中的一个或多个电容器的充电或放电的定时而不锁定在参考时钟信号的次谐波频率的I型PLL。 I型PLL的相位频率检测器（PFD）可以通过产生清零的输出信号来防止副谐波锁定，使PLL环路滤波器的采样电容仅在采样电容器未充电的时间段内放电。 例如，PFD可以包括门控元件来控制产生清除输出信号的时间。 通过确保采样电容器在充电期间的时间段内不会放电，PLL的压控振荡器被控制为以预期频率而不是预期频率的次谐波振荡。

    Phase Locked Loop with Sub-harmonic Locking Prevention Functionality
    4.
    发明申请
    Phase Locked Loop with Sub-harmonic Locking Prevention Functionality 有权
    具有次谐波锁定功能的锁相环

    公开(公告)号：US20160254818A1

    公开(公告)日：2016-09-01

    申请号：US14423422

    申请日：2014-10-23

    Applicant: LATTICE SEMICONDUCTOR CORPORATION

    Inventor： Kexin Luo ,  Yan Rui ,  Shaoyong Lu ,  Rui Yin ,  Yu Shen

    IPC: H03L7/089 ,  H03L7/18 ,  H03L7/099

    CPC classification number: H03L7/0891 ,  H03L7/089 ,  H03L7/093 ,  H03L7/099 ,  H03L7/18 ,  H03L2207/14

    Abstract: Embodiments relate to type-I PLLs that do not lock at a sub-harmonic frequency of a reference clock signal by controlling timing of charging or discharging of one or more capacitors in the PLLs. A phase frequency detector (PFD) of a type-I PLL can prevent sub-harmonic locking by generating a clear output signal to cause a sampling capacitor of PLL's loop filter to discharge only during a time period when the sampling capacitor is not being charged. For example, the PFD can include a gating element to control the time during which the clear output signal is generated. By ensuring that the sampling capacitor is not discharged during a time period while it is being charged, the PLL's voltage-controlled oscillator is controlled to oscillate at an intended frequency rather than at a sub-harmonic of the intended frequency.

    Abstract translation: 实施例涉及通过控制PLL中的一个或多个电容器的充电或放电的定时而不锁定在参考时钟信号的次谐波频率的I型PLL。 I型PLL的相位频率检测器（PFD）可以通过产生清零的输出信号来防止副谐波锁定，使PLL环路滤波器的采样电容仅在采样电容器未充电的时间段内放电。 例如，PFD可以包括门控元件来控制产生清除输出信号的时间。 通过确保采样电容器在充电期间的时间段内不会放电，PLL的压控振荡器被控制为以预期频率而不是预期频率的次谐波振荡。

    Line driver with separate pre-driver for feed-through capacitance
    5.
    发明授权
    Line driver with separate pre-driver for feed-through capacitance 有权
    线驱动器具有独立的预驱动器，用于馈通电容

    公开(公告)号：US09344081B2

    公开(公告)日：2016-05-17

    申请号：US14123037

    申请日：2013-03-15

    Applicant: Lattice Semiconductor Corporation

    Inventor： Kexin Luo ,  Fangqing Chu ,  Huaizhou Yang ,  Yu Shen ,  Inyeol Lee

    IPC: H03K17/56 ,  H04L25/02

    CPC classification number: H03K17/56 ,  H04L25/0272

    Abstract: Embodiments of the invention are generally directed to a line driver with separate pre-driver for feed-through capacitance. An embodiment of an apparatus includes a differential pair of transistors to generate an output signal on a first output node and a second output node; a pass-through capacitance coupled with the first output node and the second output node; a first pre-driver to drive an input signal for the differential transistors; and a second pre-driver to drive the input signal for the pass-through capacitance.

    Abstract translation: 本发明的实施例通常涉及具有用于馈通电容的单独的预驱动器的线路驱动器。 装置的实施例包括：差分对晶体管，用于在第一输出节点和第二输出节点上产生输出信号; 与第一输出节点和第二输出节点耦合的直通电容; 用于驱动差分晶体管的输入信号的第一预驱动器; 以及第二预驱动器来驱动所述输入信号用于所述直通电容。

    Successive Approximation Register-based Analog-to-Digital Converter with Increased Time Frame for Digital-to-Analog Capacitor Settling
    9.
    发明申请
    Successive Approximation Register-based Analog-to-Digital Converter with Increased Time Frame for Digital-to-Analog Capacitor Settling 有权
    用于数模模拟电容器稳定的逐步逼近寄存器的模数转换器具有增加的时间框架

    公开(公告)号：US20160254821A1

    公开(公告)日：2016-09-01

    申请号：US14423681

    申请日：2014-10-23

    Applicant: LATTICE SEMICONDUCTOR CORPORATION

    Inventor： Kexin Luo ,  Xiaozhi Lin ,  Guofu Peng ,  Yu Shen ,  Gijung Ahn

    IPC: H03M1/46 ,  H03K5/24

    CPC classification number: H03M1/466 ,  H03K5/2481 ,  H03M1/125

    Abstract: Embodiments relate to successive approximation register (SAR)-based analog-to-digital converters (ADCs) that increase a time frame allocated for the settling of capacitors in a digital-to-analog converter (DAC) capacitor network by feeding a comparator output signal to the DAC to begin DAC capacitor settling before the comparator output is latched by a clock signal at a latching time. The SAR ADC can include a window circuit that provides the comparator output directly from the comparator to the DAC before the latching time of the comparator. After the latching time, the latched version of the comparator output is provided to the DAC capacitor. By providing the capacitor output to the DAC capacitor before latching, DAC capacitor can settle earlier compared to an SAR ADC where DAC capacitor settling begins after the latching time of the comparator.

    Abstract translation: 实施例涉及基于逐次逼近寄存器（SAR）的模数转换器（ADC），其通过馈送比较器输出信号来增加分配用于稳定数模转换器（DAC）电容器网络中的电容器的时间帧 在DAC锁存时间之前，通过时钟信号锁存比较器输出，DAC才能开始DAC电容稳定。 SAR ADC可以包括在比较器的锁存时间之前将比较器输出直接从比较器提供给DAC的窗口电路。 锁存时间后，比较器输出的锁存版本提供给DAC电容。 通过在锁存之前将电容器输出提供给DAC电容器，与比较器的锁存时间之后DAC电容器稳定开始的SAR ADC相比，DAC电容器可以更早地稳定。

    Line driver apparatus with combined feed-through capacitance and feed-forward equalization
    10.
    发明授权
    Line driver apparatus with combined feed-through capacitance and feed-forward equalization 有权

    公开(公告)号：US10693463B2

    公开(公告)日：2020-06-23

    申请号：US15487847

    申请日：2017-04-14

    Applicant: Lattice Semiconductor Corporation

    Inventor： Kexin Luo

    IPC: H03K19/0175 ,  H04L25/08 ,  H04L25/03 ,  H03F3/45

    Abstract: Example embodiments of the present disclosure relate to a line driver apparatus. In some example embodiments, an apparatus is provided. The apparatus includes a capacitive feed-through module and a driving module. The capacitive feed-through module includes a first pre-driver operable to receive input differential signals and delayed signals of the input differential signals, generate first drive signals from the input differential signals and the delayed signals, and equalize the first drive signals. The capacitive feed-through module also includes a capacitance reducing module arranged between the first pre-driver and transmission lines and operable to reduce parasitic capacitance at the transmission lines in response to the first drive signals. The driving module is coupled to the transmission lines and operable to generate output differential signals from the input differential signals for transmission on the transmission lines.

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