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    Silicon nitride/oxygen doped silicon carbide etch stop bi-layer for improved interconnect reliability
    1.
    发明申请
    Silicon nitride/oxygen doped silicon carbide etch stop bi-layer for improved interconnect reliability 审中-公开
    氮化硅/氧掺杂碳化硅蚀刻停止双层以提高互连可靠性

    公开(公告)号：US20080014739A1

    公开(公告)日：2008-01-17

    申请号：US11475924

    申请日：2006-06-28

    申请人： Laura M. Matz ,  Asad Haider ,  Robert Kraft

    发明人： Laura M. Matz ,  Asad Haider ,  Robert Kraft

    IPC分类号： H01L21/4763 ,  H01L23/52 ,  H01L23/48 ,  H01L29/40

    CPC分类号： H01L23/53295 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In accordance with the invention, there are semiconductor devices and methods for making semiconductor devices and film stacks in an integrated circuits. The method of making a semiconductor device can comprise forming a semiconductor structure comprising at least one copper interconnect, forming an etch stop bi-layer comprising a first layer and a second layer, wherein the first layer comprising silicon nitride is disposed over the semiconductor structure comprising at least one copper interconnect, and the second layer comprising silicon oxy-carbide is disposed over the first layer, and depositing a dielectric layer over the etch stop bi-layer.

    摘要翻译： 根据本发明，存在用于在集成电路中制造半导体器件和薄膜叠层的半导体器件和方法。 制造半导体器件的方法可以包括形成包括至少一个铜互连的半导体结构，形成包括第一层和第二层的蚀刻停止双层，其中包含氮化硅的第一层设置在半导体结构之上，包括 至少一个铜互连，并且包含碳化硅碳的第二层设置在第一层之上，并且在蚀刻停止双层上沉积介电层。

    Simultaneous deposition and etch process for barrier layer formation in microelectronic device interconnects
    2.
    发明申请
    Simultaneous deposition and etch process for barrier layer formation in microelectronic device interconnects 有权
    用于微电子器件互连中阻挡层形成的同时沉积和蚀刻工艺

    公开(公告)号：US20060258142A1

    公开(公告)日：2006-11-16

    申请号：US11126460

    申请日：2005-05-11

    申请人： Asad Haider ,  Alfred Griffin ,  Kelly Taylor

    发明人： Asad Haider ,  Alfred Griffin ,  Kelly Taylor

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76865 ,  Y10S438/905

    摘要： The present invention provides a method of forming a interconnect barrier layer 100. The method comprises physical vapor deposition of barrier material 200 within an opening 140 located in a dielectric layer 135 of a substrate 110. The method also comprises a RF plasma etching the barrier material 200 deposited in the opening 140 simultaneously with conducting the physical vapor deposition of the barrier material 200.

    摘要翻译： 本发明提供一种形成互连阻挡层100的方法。 该方法包括将阻挡材料200物理气相沉积在位于衬底110的电介质层135内的开口140内。 该方法还包括RF等离子体蚀刻沉积在开口140中的阻挡材料200，同时进行阻挡材料200的物理气相沉积。

    System and method to form improved seed layer
    3.
    发明申请
    System and method to form improved seed layer 审中-公开
    系统和方法形成改良种子层

    公开(公告)号：US20060014378A1

    公开(公告)日：2006-01-19

    申请号：US10890663

    申请日：2004-07-14

    申请人： Sanjeev Aggarwal ,  Kelly Taylor ,  Asad Haider ,  Alfred Griffin

    发明人： Sanjeev Aggarwal ,  Kelly Taylor ,  Asad Haider ,  Alfred Griffin

    IPC分类号： H01L21/4763 ,  H01L21/44

    CPC分类号： H01L21/76843 ,  H01L21/2855 ,  H01L21/76865 ,  H01L21/76873

    摘要： A method is disclosed to form a seed layer for an integrated circuit. The method may include depositing a metal seed layer (106) over a barrier layer (104) such that the metal seed layer (106) has a greater thickness along a top surface portion (114) of at least one recessed feature (102) formed in the substrate that is substantially coplanar with the substrate than a sidewall surface portion (112) of the at least one recessed feature (102). A portion of the metal seed layer (106) is etched from the top surface portion (114) of the at least one recessed feature (102) to improve coverage of the metal seed layer (106) along the sidewall surface portion (112) of the at least one recessed feature (102) and to mitigate overhang of the metal seed layer.

    摘要翻译： 公开了形成用于集成电路的种子层的方法。 该方法可以包括在阻挡层（104）上沉积金属种子层（106），使得金属籽晶层（106）沿着形成的至少一个凹形特征（102）的顶表面部分（114）具有更大的厚度 在与所述至少一个凹陷特征（102）的侧壁表面部分（112）基本共面的基底中。 从所述至少一个凹陷特征（102）的顶表面部分（114）蚀刻所述金属种子层（106）的一部分，以改善所述金属种子层（106）沿着所述侧壁表面部分（112）的覆盖范围 所述至少一个凹陷特征（102）并且减轻所述金属种子层的突出部分。

    Novel barrier integration scheme for high-reliability vias
    4.
    发明申请
    Novel barrier integration scheme for high-reliability vias 审中-公开
    高可靠性通孔的新型屏障整合方案

    公开(公告)号：US20060009030A1

    公开(公告)日：2006-01-12

    申请号：US11175174

    申请日：2005-07-07

    申请人： Alfred Griffin ,  Edmund Burke ,  Asad Haider ,  Kelly Taylor ,  Tae Kim

    发明人： Alfred Griffin ,  Edmund Burke ,  Asad Haider ,  Kelly Taylor ,  Tae Kim

    IPC分类号： H01L21/4763 ,  H01L21/44

    CPC分类号： H01L21/76802 ,  H01L21/02063 ,  H01L21/2855 ,  H01L21/32131 ,  H01L21/76805 ,  H01L21/76829 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76847 ,  H01L21/76867 ,  H01L23/5226 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Disclosed is a method of fabricating an integrated circuit comprising patterning a dielectric layer to form a hole having a sidewall and a bottom. The hole can expose an underlying material of an electrically conducting material. The method also includes exposing the sidewall and the exposed underlying material to a plasma etch, depositing a barrier layer on the bottom and the sidewall of the hole after the plasma etch clean, forming a counter-sunk cone in the underlying material by etching through the barrier layer at the bottom of the hole into the conducting metal underneath, flash depositing a thin layer of the barrier material into the hole, and finally depositing a metal seed layer in the hole covering the sidewalls and the bottom of the hole including the cone at the bottom. The hole is finally filled by depositing a metal layer in the hole.

    摘要翻译： 公开了一种制造集成电路的方法，包括图案化介电层以形成具有侧壁和底部的孔。 孔可以暴露导电材料的下层材料。 该方法还包括将侧壁和暴露的下层材料暴露于等离子体蚀刻，在等离子体蚀刻清洁之后，在孔的底部和侧壁上沉积阻挡层，在下面的材料中通过蚀刻通过 在孔的底部的阻挡层进入下面的导电金属，将阻挡材料的薄层快速沉积到孔中，最后在覆盖包括锥体的孔的侧壁和底部的孔中沉积金属种子层 底端。 最后通过在孔中沉积金属层来填充孔。

    Recess reduction for leakage improvement in high density capacitors
    5.
    发明申请
    Recess reduction for leakage improvement in high density capacitors 审中-公开
    高密度电容器的漏电改善减少

    公开(公告)号：US20050233563A1

    公开(公告)日：2005-10-20

    申请号：US10825351

    申请日：2004-04-15

    申请人： Lindsey Hall ,  Satyavolu Papa Rao ,  Gad Haase ,  Asad Haider

    发明人： Lindsey Hall ,  Satyavolu Papa Rao ,  Gad Haase ,  Asad Haider

    IPC分类号： H01L21/02 ,  H01L21/331 ,  H01L21/44 ,  H01L21/768 ,  H01L21/8222 ,  H01L27/06

    CPC分类号： H01L28/40 ,  H01L21/7684 ,  H01L27/0629

    摘要： The present invention provides a capacitor [205]. The capacitor [205] includes a first conductive layer [206] located on an interconnect structure [226] formed in a dielectric layer [228], a capacitor dielectric layer [208] located over the first conductive layer [206] and a second conductive layer [210] located over the capacitor dielectric layer [208]. The recess relief in the surface of the dielectric layer [228] attributable to a fabrication process has been reduced about the interconnect structure [226] to provide a more planar deposition surface over which the capacitor's [205] layers may be deposited.

    摘要翻译： 本发明提供一种电容器[205]。 电容器[205]包括位于形成在介电层[228]中的互连结构[226]上的第一导电层[206]，位于第一导电层[206]上方的电容器介电层[208]和第二导电层 位于电容器介电层[208]上方的层[210]。 由于制造工艺导致的电介质层[228]表面的凹陷已经围绕互连结构[226]减小，以提供更平坦的沉积表面，电容器的[205]层可以沉积在该平面上。

    Process and integration scheme for a high sidewall coverage ultra-thin metal seed layer
    9.
    发明申请
    Process and integration scheme for a high sidewall coverage ultra-thin metal seed layer 有权
    高侧壁覆盖超薄金属种子层的工艺和集成方案

    公开(公告)号：US20060258152A1

    公开(公告)日：2006-11-16

    申请号：US11126413

    申请日：2005-05-11

    申请人： Asad Haider

    发明人： Asad Haider

    IPC分类号： H01L21/4763 ,  H01L21/44

    CPC分类号： H01L21/2855 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76873

    摘要： The present invention provides a method of forming a metal seed layer 100. The method comprises physical vapor deposition of seed metal 200 within an opening 140 located in a dielectric layer 135 of a substrate 110. The method also comprises a RF plasma etch of the seed metal 200 deposited in the opening 140 simultaneously with conducting the physical vapor deposition of the seed metal 200.

    摘要翻译： 本发明提供一种形成金属种子层100的方法。 该方法包括种子金属200在位于衬底110的电介质层135内的开口140内的物理气相沉积。 该方法还包括沉积在开口140中的种子金属200的RF等离子体蚀刻，同时进行种子金属200的物理气相沉积。

    Process for using a high nitrogen concentration plasma for fluorine removal from a reactor
    10.
    发明授权
    Process for using a high nitrogen concentration plasma for fluorine removal from a reactor 有权
    使用高氮浓度等离子体从反应器中除去氟的方法

    公开(公告)号：US06467490B1

    公开(公告)日：2002-10-22

    申请号：US09382917

    申请日：1999-08-25

    申请人： Hidenori Kawata ,  Asad Haider

    发明人： Hidenori Kawata ,  Asad Haider

    IPC分类号： B08B600

    CPC分类号： H01J37/32862 ,  C23C16/4405

    摘要： A process of removing fluorine from a chemical deposition reactor includes the step of injecting a gaseous mixture of nitrogen and hydrogen into the reactor, the volume ratio of nitrogen to hydrogen in the gaseous mixture being in the range of from 1:1 to 6:1. More preferably the N2/H2 ratio is in the range of 2.5 to 4.5:1. The gaseous mixture is ionized with a RF induced energy discharge, with a RF power setting typically in the range of from 200 to 250 watts at an RF frequency of 13.5 MHZ. The gaseous mixture is injected into the reactor for a predetermined period of time based upon the thickness of a material, typically a metal such as tungsten, deposited upon a wafer in the reactor during a semiconductor fabrication process.

    摘要翻译： 从化学沉积反应器除去氟的方法包括将氮气和氢气的气态混合物注入反应器的步骤，气体混合物中氮与氢的体积比在1:1至6:1的范围内 。 更优选地，N 2 / H 2比在2.5至4.5:1的范围内。 气体混合物用RF感应能量放电电离，RF功率设置通常在13.5MHz的RF频率范围内为200-250瓦特。 基于在半导体制造过程中沉积在反应器中的晶片上的材料（通常为诸如钨的金属）的厚度，将气态混合物注入反应器预定的时间段。