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    FABRICATION OF A DIFFUSION BARRIER CAP ON COPPER CONTAINING CONDUCTIVE ELEMENTS
    6.
    发明申请
    FABRICATION OF A DIFFUSION BARRIER CAP ON COPPER CONTAINING CONDUCTIVE ELEMENTS 有权
    包含导电元件的扩散阻挡层的制造

    公开(公告)号：US20100044865A1

    公开(公告)日：2010-02-25

    申请号：US12516127

    申请日：2007-11-27

    申请人： Joaquin Torres ,  Laurent Gosset ,  Vincent Arnal ,  Sonarith Chhun

    发明人： Joaquin Torres ,  Laurent Gosset ,  Vincent Arnal ,  Sonarith Chhun

    IPC分类号： H01L21/768 ,  H01L23/48

    CPC分类号： H01L21/76849 ,  H01L21/7682 ,  H01L21/76822 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76856 ,  H01L21/76867 ,  H01L21/76886 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for fabricating a self-aligned diffusion-barrier cap on a Cu-containing conductive element in an integrated-circuit device comprises:—providing a substrate having a Cu-containing conductive element embedded laterally into a dielectric layer and having an exposed surface;—depositing a metal layer on the exposed surface of conductive element;—inducing diffusion of metal from the metal layer into a top section of the conductive element;—removing the remaining metal layer;—letting diffused metal in the top section of the conductive element and particles of a second constituent react with each other so as to build a compound covering the conductive element. The metal of the metal layer and the second constituent are chosen so that the compound forms a diffusion barrier against Cu diffusion. A reduction the dielectric constant of the dielectric material in an interconnect stack of an integrated-circuit device is achieved.

    摘要翻译： 一种用于在集成电路器件中的含Cu导电元件上制造自对准扩散阻挡帽的方法包括： - 将具有横向嵌入电介质层并具有暴露表面的含Cu导电元件的衬底提供; - 将金属层沉积在导电元件的暴露表面上; - 将金属从金属层扩散到导电元件的顶部; - 移除剩余的金属层; - 在导电元件的顶部中引入扩散金属 并且第二组分的颗粒彼此反应，以便构成覆盖导电元件的化合物。 选择金属层和第二组分的金属，使得该化合物形成针对Cu扩散的扩散阻挡层。 实现了集成电路器件的互连叠层中介电材料的介电常数的降低。

    Formation of a reliable diffusion-barrier cap on a Cu-containing interconnect element having grains with different crystal orientations
    7.
    发明授权
    Formation of a reliable diffusion-barrier cap on a Cu-containing interconnect element having grains with different crystal orientations 有权
    在具有不同晶体取向的晶粒的含Cu互连元件上形成可靠的扩散阻挡帽

    公开(公告)号：US07989342B2

    公开(公告)日：2011-08-02

    申请号：US12529647

    申请日：2008-03-03

    申请人： Joaquin Torres ,  Laurent Gosset ,  Sonarith Chhun ,  Vincent Arnal

    发明人： Joaquin Torres ,  Laurent Gosset ,  Sonarith Chhun ,  Vincent Arnal

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76849 ,  H01L21/76834 ,  H01L21/76867 ,  H01L21/76889

    摘要： The present invention relates to a method for fabricating a diffusion-barrier cap on a Cu-containing interconnect element that has crystallites of at least two different crystal orientations, comprises selectively incorporating Si into only a first set of crystallites with at least one first crystal orientation, employing first process conditions, and subsequently selectively forming a first adhesion-layer portion comprising CuSi and a first diffusion-barrier-layer portion only on the first set of crystallites, thus forming a first barrier-cap portion, and subsequently selectively incorporating Si into only the second set of crystallites, employing second process conditions that differ from the first process conditions, and forming a second barrier-cap portion comprising a Si-containing second diffusion-barrier layer portion on the second set of crystallites of the interconnect element. The processing improves the properties of the diffusion-barrier cap and secures a continuous formation of a diffusion-barrier layer on the interconnect element.

    摘要翻译： 本发明涉及一种在具有至少两种不同晶体取向的微晶的含Cu互连元件上制造扩散阻挡帽的方法，包括选择性地将Si掺入到仅具有至少一个第一晶体取向的第一组微晶中 采用第一工艺条件，随后在第一组微晶上选择性地形成包含CuSi和第一扩散阻挡层部分的第一粘附层部分，从而形成第一阻挡帽部分，随后选择性地将Si并入 仅使用第二组微晶，采用与第一工艺条件不同的第二工艺条件，以及在互连元件的第二组微晶上形成包含含Si的第二扩散阻挡层部分的第二阻挡帽部分。 该处理改善了扩散阻挡帽的性质，并确保了互连元件上的扩散阻挡层的连续形成。

    Fabrication of a diffusion barrier cap on copper containing conductive elements
    8.
    发明授权
    Fabrication of a diffusion barrier cap on copper containing conductive elements 有权
    在含铜导电元件上制造扩散阻挡帽

    公开(公告)号：US08143157B2

    公开(公告)日：2012-03-27

    申请号：US12516127

    申请日：2007-11-27

    申请人： Joaquin Torres ,  Laurent Gosset ,  Vincent Arnal ,  Sonarith Chhun

    发明人： Joaquin Torres ,  Laurent Gosset ,  Vincent Arnal ,  Sonarith Chhun

    IPC分类号： H01L21/4763 ,  H01L23/48

    CPC分类号： H01L21/76849 ,  H01L21/7682 ,  H01L21/76822 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76856 ,  H01L21/76867 ,  H01L21/76886 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for fabricating a self-aligned diffusion-barrier cap on a Cu-containing conductive element in an integrated-circuit device comprises:—providing a substrate having a Cu-containing conductive element embedded laterally into a dielectric layer and having an exposed surface;—depositing a metal layer on the exposed surface of conductive element;—inducing diffusion of metal from the metal layer into a top section of the conductive element;—removing the remaining metal layer;—letting diffused metal in the top section of the conductive element and particles of a second constituent react with each other so as to build a compound covering the conductive element. The metal of the metal layer and the second constituent are chosen so that the compound forms a diffusion barrier against Cu diffusion. A reduction the dielectric constant of the dielectric material in an interconnect stack of an integrated-circuit device is achieved.

    摘要翻译： 一种用于在集成电路器件中的含Cu导电元件上制造自对准扩散阻挡帽的方法包括： - 将具有横向嵌入电介质层并具有暴露表面的含Cu导电元件的衬底提供; - 将金属层沉积在导电元件的暴露表面上; - 将金属从金属层扩散到导电元件的顶部; - 移除剩余的金属层; - 在导电元件的顶部中引入扩散金属 并且第二组分的颗粒彼此反应，以便构成覆盖导电元件的化合物。 选择金属层和第二组分的金属，使得该化合物形成针对Cu扩散的扩散阻挡层。 实现了集成电路器件的互连叠层中介电材料的介电常数的降低。

    FORMATION OF A RELIABLE DIFFUSION-BARRIER CAP ON A CU-CONTAINING INTERCONNECT ELEMENT HAVING GRAINS WITH DIFFERENT CRYSTAL ORIENTATIONS
    9.
    发明申请
    FORMATION OF A RELIABLE DIFFUSION-BARRIER CAP ON A CU-CONTAINING INTERCONNECT ELEMENT HAVING GRAINS WITH DIFFERENT CRYSTAL ORIENTATIONS 有权
    在具有不同晶体取向的颗粒的含CU连接元件上形成可靠的扩散阻挡层

    公开(公告)号：US20100120243A1

    公开(公告)日：2010-05-13

    申请号：US12529647

    申请日：2008-03-03

    申请人： Joaquin Torres ,  Laurent Gosset ,  Sonarith Chhun ,  Vincent Arnal

    发明人： Joaquin Torres ,  Laurent Gosset ,  Sonarith Chhun ,  Vincent Arnal

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76849 ,  H01L21/76834 ,  H01L21/76867 ,  H01L21/76889

    摘要： The present invention relates to a method for fabricating a diffusion-barrier cap on a Cu-containing interconnect element that has crystallites of at least two different crystal orientations, comprises selectively incorporating Si into only a first set of crystallites with at least one first crystal orientation, employing first process conditions, and subsequently selectively forming a first adhesion-layer portion comprising CuSi and a first diffusion-barrier-layer portion only on the first set of crystallites, thus forming a first barrier-cap portion, and subsequently selectively incorporating Si into only the second set of crystallites, employing second process conditions that differ from the first process conditions, and forming a second barrier-cap portion comprising a Si-containing second diffusion-barrier layer portion on the second set of crystallites of the interconnect element. The processing improves the properties of the diffusion-barrier cap and secures a continuous formation of a diffusion-barrier layer on the interconnect element.

    摘要翻译： 本发明涉及一种在具有至少两种不同晶体取向的微晶的含Cu互连元件上制造扩散阻挡帽的方法，包括选择性地将Si掺入到仅具有至少一个第一晶体取向的第一组微晶中 采用第一工艺条件，随后在第一组微晶上选择性地形成包含CuSi和第一扩散阻挡层部分的第一粘附层部分，从而形成第一阻挡帽部分，随后选择性地将Si并入 仅使用第二组微晶，采用与第一工艺条件不同的第二工艺条件，以及在互连元件的第二组微晶上形成包含含Si的第二扩散阻挡层部分的第二阻挡帽部分。 该处理改善了扩散阻挡帽的性质，并且确保了互连元件上的扩散阻挡层的连续形成。

    METHOD OF FORMING A LAYER OVER A SURFACE OF A FIRST MATERIAL EMBEDDED IN A SECOND MATERIAL IN A STRUCTURE FOR A SEMICONDUCTOR DEVICE
    10.
    发明申请
    METHOD OF FORMING A LAYER OVER A SURFACE OF A FIRST MATERIAL EMBEDDED IN A SECOND MATERIAL IN A STRUCTURE FOR A SEMICONDUCTOR DEVICE 审中-公开
    在半导体器件结构中嵌入第二材料中的第一材料的表面上形成层的方法

    公开(公告)号：US20090197405A1

    公开(公告)日：2009-08-06

    申请号：US12096231

    申请日：2006-12-04

    申请人： Wim Besling ,  Sonarith Chhun

    发明人： Wim Besling ,  Sonarith Chhun

    IPC分类号： H01L21/768

    CPC分类号： H01L21/76849 ,  H01L21/28562 ,  H01L21/76801 ,  H01L21/76826 ,  H01L21/76828

    摘要： There is described a method of forming a barrier layer (6, 110) over a surface of a copper line (3, 107) embedded in a dielectric material (2, 100) in an interconnect structure for a semiconductor device. The barrier layer (6, 110) is selectively deposited over the surface of the copper line (3, 107) by a vapour deposition step and the surface of the dielectric material (2, 100) is treated prior to the vapour deposition step to inhibit deposition of the barrier layer (6, 110) there on during the vapour deposition step. Preferably, the vapour deposition step comprises atomic layer deposition.

    摘要翻译： 描述了在半导体器件的互连结构中嵌入在电介质材料（2,100）中的铜线（3,107）的表面上形成阻挡层（6,110）的方法。 通过气相沉积步骤在铜线（3,107）的表面上选择性地沉积阻挡层（6,110），并且在气相沉积步骤之前处理电介质材料（2,100）的表面以抑制 在气相沉积步骤期间在其上沉积阻挡层（6,110）。 优选地，气相沉积步骤包括原子层沉积。