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公开(公告)号：US07092235B2
公开(公告)日：2006-08-15
申请号：US11043760
申请日：2005-01-26
申请人： Lawrence A. Clevenger , Timothy J. Dalton , Louis L. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Timothy J. Dalton , Louis L. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01G4/06
摘要： A method and apparatus, is herein disclosed, for adjusting capacitance of an on-chip capacitor formed on a substrate. A plurality of conductive layers is separated by a layer ofdielectric material. The dielectric material of the capacitor is exposed to an ion beam. The ion beam includes ions of at least one material to modify a dielectric constant of the dielectric material.
摘要翻译： 本文公开了一种用于调节形成在衬底上的片上电容器的电容的方法和装置。 多个导电层被一层电介质材料隔开。 电容器的电介质材料暴露于离子束。 离子束包括至少一种材料的离子，以改变介电材料的介电常数。
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公开(公告)号：US06869895B1
公开(公告)日：2005-03-22
申请号：US10674719
申请日：2003-09-30
申请人： Lawrence A. Clevenger , Timothy J. Dalton , Louis L. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Timothy J. Dalton , Louis L. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
摘要： A method and apparatus for adjusting capacitance of an on-chip capacitor uses exposure of a dielectric material of the capacitor to an ion beam comprising ions of at least one material to modify a dielectric constant of the dielectric material.
摘要翻译： 用于调整片上电容器的电容的方法和装置使用将电容器的电介质材料暴露于包含至少一种材料的离子的离子束，以改变介电材料的介电常数。
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公开(公告)号：US20080308801A1
公开(公告)日：2008-12-18
申请号：US12193288
申请日：2008-08-18
申请人： Lawrence A. Clevenger , Matthew E. Colburn , Timothy J. Dalton , Michael C. Gaidis , Louis L. C. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Matthew E. Colburn , Timothy J. Dalton , Michael C. Gaidis , Louis L. C. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L23/58
CPC分类号： H01L23/576 , H01L21/31144 , H01L23/544 , H01L28/20 , H01L28/40 , H01L2223/54433 , H01L2223/5444 , H01L2924/0002 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/00
摘要： A method of forming a stochastically based integrated circuit encryption structure includes forming a lower conductive layer over a substrate, forming a short prevention layer over the lower conductive layer, forming an intermediate layer over the short prevention layer, wherein the intermediate layer is characterized by randomly structured nanopore features. An upper conductive layer is formed over the random nanopore structured intermediate layer. The upper conductive layer is patterned into an array of individual cells, wherein a measurable electrical parameter of the individual cells has a random distribution from cell to cell with respect to a reference value of the electrical parameter.
摘要翻译： 一种形成随机的集成电路加密结构的方法包括在衬底上形成下导电层，在下导电层上形成防短层，在短路防护层上形成中间层，其中中间层的特征是随机 结构纳米孔特征。 在无规纳米孔结构化中间层上形成上导电层。 上导电层被图案化成单个单元的阵列，其中各个单元的可测量电参数相对于电参数的参考值具有从单元到单元的随机分布。
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4.发明申请HIGH DENSITY PLANAR MAGNETIC DOMAIN WALL MEMORY APPARATUS AND METHOD OF FORMING THE SAME 有权高密度平面磁畴壁记忆装置及其形成方法公开(公告)号：US20080243972A1
公开(公告)日：2008-10-02
申请号：US11694183
申请日：2007-03-30
申请人： Michael C. Gaidis , Lawrence A. Clevenger , Timothy J. Dalton , John K. DeBrosse , Louis L.C. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Michael C. Gaidis , Lawrence A. Clevenger , Timothy J. Dalton , John K. DeBrosse , Louis L.C. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： G06F15/02
CPC分类号： G11C19/0841 , B82Y10/00 , G11C5/02 , G11C11/161 , G11C11/1675 , Y10T29/53165
摘要： A magnetic domain wall memory apparatus with write/read capability includes a plurality of coplanar shift register structures each comprising an elongated track formed from a ferromagnetic material having a plurality of magnetic domains therein, the shift register structures further having a plurality of discontinuities therein to facilitate domain wall location; a magnetic read element associated with each of the shift register structures; and a magnetic write element associated with each of the shift register structures, the magnetic write element further comprising a single write wire having a longitudinal axis substantially orthogonal to a longitudinal axis of each of the coplanar shift register structures.
摘要翻译： 具有写入/读取功能的磁畴壁存储装置包括多个共面移位寄存器结构，每个包括由其中具有多个磁畴的铁磁材料形成的细长轨道，移位寄存器结构还具有多个不连续性，以便于 域墙位置; 与每个移位寄存器结构相关联的磁读取元件; 以及与所述移位寄存器结构中的每一个相关联的磁写元件，所述磁写入元件还包括单个写入线，所述单个写入线的纵轴基本上与所述共面移位寄存器结构中的每一个的纵向轴线正交。
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公开(公告)号：US07514271B2
公开(公告)日：2009-04-07
申请号：US11694183
申请日：2007-03-30
申请人： Michael C. Gaidis , Lawrence A. Clevenger , Timothy J. Dalton , John K. DeBrosse , Louis L. C. Hsu , Carl Radens , Keith Kwong-Hon Wong , Chih-Chao Yang
发明人： Michael C. Gaidis , Lawrence A. Clevenger , Timothy J. Dalton , John K. DeBrosse , Louis L. C. Hsu , Carl Radens , Keith Kwong-Hon Wong , Chih-Chao Yang
CPC分类号： G11C19/0841 , B82Y10/00 , G11C5/02 , G11C11/161 , G11C11/1675 , Y10T29/53165
摘要： A method of forming a magnetic domain wall memory apparatus with write/read capability includes forming a plurality of coplanar shift register structures each comprising an elongated track formed from a ferromagnetic material having a plurality of magnetic domains therein, the shift register structures further having a plurality of discontinuities therein to facilitate domain wall location: forming a magnetic read element associated with each of the shift register structures: and forming a magnetic write element associated with each of the shift register structures, the magnetic write element further comprising a write wire having a constriction therein, the constriction located at a point corresponding to the location of one of the plurality of discontinuities in the associated shift register structure.
摘要翻译： 形成具有写入/读取能力的磁畴壁存储装置的方法包括形成多个共面移位寄存器结构，每个包括由其中具有多个磁畴的铁磁材料形成的细长轨道，移位寄存器结构还具有多个 其中的不连续性以便于域壁位置：形成与每个移位寄存器结构相关联的磁读取元件;以及形成与每个移位寄存器结构相关联的磁写元件，所述磁写入元件还包括具有收缩的写入线 其中，所述收缩部位于与相关联的移位寄存器结构中的所述多个不连续之一的位置相对应的点处。
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公开(公告)号：US07825420B2
公开(公告)日：2010-11-02
申请号：US12539942
申请日：2009-08-12
申请人： Michael C. Gaidis , Carl Radens , Lawrence A. Clevenger , Timothy J. Dalton , Louis L. C. Hsu , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Michael C. Gaidis , Carl Radens , Lawrence A. Clevenger , Timothy J. Dalton , Louis L. C. Hsu , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L29/94
CPC分类号： B82Y10/00 , H01L27/222 , H01L43/12
摘要： A magnetic random access memory (MRAM) device includes a magnetic tunnel junction (MTJ) stack formed over a lower wiring level, a hardmask formed on the MTJ stack, and an upper wiring level formed over the hardmask. The upper wiring level includes a slot via bitline formed therein, the slot via bitline in contact with the hardmask and in contact with an etch stop layer partially surrounding sidewalls of the hardmask.
摘要翻译： 磁性随机存取存储器（MRAM）器件包括形成在下布线层上的磁隧道结（MTJ）堆叠，形成在MTJ堆叠上的硬掩模和形成在硬掩模上的上布线层。 上布线层包括经由位于其中的位线的槽，槽经由与硬掩模接触的位线并与部分地围绕硬掩模的侧壁的蚀刻停止层接触。
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7.发明授权公开(公告)号：US07635884B2
公开(公告)日：2009-12-22
申请号：US11193660
申请日：2005-07-29
申请人： Michael C. Gaidis , Carl Radens , Lawrence A. Clevenger , Timothy J. Dalton , Louis L. C. Hsu , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Michael C. Gaidis , Carl Radens , Lawrence A. Clevenger , Timothy J. Dalton , Louis L. C. Hsu , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L29/94
CPC分类号： B82Y10/00 , H01L27/222 , H01L43/12
摘要： A magnetic random access memory (MRAM) device includes a magnetic tunnel junction (MTJ) stack formed over a lower wiring level, a hardmask formed on the MTJ stack, and an upper wiring level formed over the hardmask. The upper wiring level includes a slot via bitline formed therein, the slot via bitline in contact with the hardmask and in contact with an etch stop layer partially surrounding sidewalls of the hardmask.
摘要翻译： 磁性随机存取存储器（MRAM）器件包括形成在下布线层上的磁隧道结（MTJ）堆叠，形成在MTJ堆叠上的硬掩模和形成在硬掩模上的上布线层。 上布线层包括经由位于其中的位线的槽，槽经由与硬掩模接触的位线并与部分地围绕硬掩模的侧壁的蚀刻停止层接触。
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公开(公告)号：US20080239785A1
公开(公告)日：2008-10-02
申请号：US12136089
申请日：2008-06-10
申请人： Michael C. Gaidis , Lawrence A. Clevenger , Timothy J. Dalton , John K. DeBrosse , Louis L.C. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Michael C. Gaidis , Lawrence A. Clevenger , Timothy J. Dalton , John K. DeBrosse , Louis L.C. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： G11C19/02
CPC分类号： G11C19/0841 , B82Y10/00 , G11C5/02 , G11C11/161 , G11C11/1675 , Y10T29/53165
摘要： A magnetic domain wall memory apparatus with write/read capability includes a plurality of coplanar shift register structures each comprising an elongated track formed from a ferromagnetic material having a plurality of magnetic domains therein, the shift register structures further having a plurality of discontinuities therein to facilitate domain wall location; a magnetic read element associated with each of the shift register structures; and a magnetic write element associated with each of the shift register structures, the magnetic write element further comprising a write wire having a constriction therein, the constriction located at a point corresponding to the location of the plurality of discontinuities in the associated shift register structure.
摘要翻译： 具有写入/读取功能的磁畴壁存储装置包括多个共面移位寄存器结构，每个包括由其中具有多个磁畴的铁磁材料形成的细长轨道，移位寄存器结构还具有多个不连续性，以便于 域墙位置; 与每个移位寄存器结构相关联的磁读取元件; 以及与所述移位寄存器结构中的每一个相关联的磁写元件，所述磁写入元件还包括其中具有收缩部的写入线，所述收缩部位于与相关联的移位寄存器结构中的所述多个不连续点的位置对应的点处。
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9.发明申请公开(公告)号：US20080157314A1
公开(公告)日：2008-07-03
申请号：US11619196
申请日：2007-01-03
申请人： Lawrence A. Clevenger , Matthew E. Colburn , Timothy J. Dalton , Michael C. Gaidis , Louis L. C. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Matthew E. Colburn , Timothy J. Dalton , Michael C. Gaidis , Louis L. C. Hsu , Carl Radens , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L23/02
CPC分类号： H01L23/576 , H01L21/31144 , H01L23/544 , H01L28/20 , H01L28/40 , H01L2223/54433 , H01L2223/5444 , H01L2924/0002 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/00
摘要： A method of forming a stochastically based integrated circuit encryption structure includes forming a lower conductive layer over a substrate, forming a short prevention layer over the lower conductive layer, forming an intermediate layer over the short prevention layer, wherein the intermediate layer is characterized by randomly structured nanopore features. An upper conductive layer is formed over the random nanopore structured intermediate layer. The upper conductive layer is patterned into an array of individual cells, wherein a measurable electrical parameter of the individual cells has a random distribution from cell to cell with respect to a reference value of the electrical parameter.
摘要翻译： 一种形成随机的集成电路加密结构的方法包括在衬底上形成下导电层，在下导电层上形成防短层，在短路防护层上形成中间层，其中中间层的特征是随机 结构纳米孔特征。 在无规纳米孔结构化中间层上形成上导电层。 上导电层被图案化成单个单元的阵列，其中各个单元的可测量电参数相对于电参数的参考值具有从单元到单元的随机分布。
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公开(公告)号：US08023305B2
公开(公告)日：2011-09-20
申请号：US12136091
申请日：2008-06-10
申请人： Michael C. Gaidis , Lawrence A. Clevenger , Timothy J. Dalton , John K. DeBrosse , Louis L. C. Hsu , Carl Radens , Keith Kwong-Hon Wong , Chih-Chao Yang
发明人： Michael C. Gaidis , Lawrence A. Clevenger , Timothy J. Dalton , John K. DeBrosse , Louis L. C. Hsu , Carl Radens , Keith Kwong-Hon Wong , Chih-Chao Yang
CPC分类号： G11C19/0841 , B82Y10/00 , G11C5/02 , G11C11/161 , G11C11/1675 , Y10T29/53165
摘要： A magnetic domain wall memory apparatus with write/read capability includes a plurality of coplanar shift register structures each comprising an elongated track formed from a ferromagnetic material having a plurality of magnetic domains therein, the shift register structures further having a plurality of discontinuities therein to facilitate domain wall location; a magnetic read element associated with each of the shift register structures; and a magnetic write element associated with each of the shift register structures, the magnetic write element further comprising a single write wire having a longitudinal axis substantially orthogonal to a longitudinal axis of each of the coplanar shift register structures.
摘要翻译： 具有写入/读取功能的磁畴壁存储装置包括多个共面移位寄存器结构，每个包括由其中具有多个磁畴的铁磁材料形成的细长轨道，移位寄存器结构还具有多个不连续性，以便于 域墙位置; 与每个移位寄存器结构相关联的磁读取元件; 以及与所述移位寄存器结构中的每一个相关联的磁写元件，所述磁写入元件还包括单个写入线，所述单个写入线的纵轴基本上与所述共面移位寄存器结构中的每一个的纵向轴线正交。
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